Product Information

74LVC841AD,118

74LVC841AD,118 electronic component of Nexperia

Datasheet
Latches 10BIT BUS INTERFC
Manufacturer: Nexperia
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Price (USD)

1: USD 1.1907 ea
Line Total: USD 1.19

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1

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Ships to you between Thu. 09 May to Wed. 15 May

MOQ : 100
Multiples : 1

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74LVC841AD,118
Nexperia

100 : USD 0.745
500 : USD 0.6757
1000 : USD 0.4741
2500 : USD 0.4433
5000 : USD 0.4292

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Product Category
RoHS - XON
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Number of Circuits
Logic Type
Logic Family
Polarity
Quiescent Current
Number of Output Lines
High Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
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Additional Infomation About Product

74LVC841A 10-bit transparent latch with 5 V tolerant inputs/outputs 3-state Rev. 4 2 April 2013 Product data sheet 1. General description The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus applications. A latch enable (pin LE) input and an output enable (pin OE) input are common to all internal latches. The device consists of ten transparent latches with 3-state true outputs. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output changes each time its corresponding D-input changes. When pin LE is LOW, the latches store the information that was present at the D-inputs a set-up time preceding the HIGH to LOW transition of pin LE. When pin OE is LOW, the contents of the ten latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the pin OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Flow-through pinout architecture Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 Cto+85 C and 40 Cto+125 C.74LVC841A NXP Semiconductors 10-bit transparent latch with 5 V tolerant inputs/outputs 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74LVC841AD 40 Cto +125 C SO24 plastic small outline package 24 leads SOT137-1 body width 7.5 mm 74LVC841ADB 40 Cto +125 C SSOP24 plastic shrink small outline package 24 leads SOT340-1 body width 5.3 mm 74LVC841APW 40 Cto +125 C TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm 74LVC841ABQ 40 Cto +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1 thin quad flat package no leads 24 terminals body 3.5 x 5.5 x 0.85 mm 4. Functional diagram 2 D0 Q0 23 3 D1 Q1 22 4 D2 Q2 21 5 D3 Q3 20 6 D4 Q4 19 LATCH 3-STATE 7 D5 Q5 18 1 TO 8 OUTPUTS 8 D6 Q6 17 9 D7 Q7 16 10 D8 Q8 15 11 D9 Q9 14 13 LE 1 OE 001aaa842 Fig 1. Functional diagram 74LVC841A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 2 April 2013 2 of 20

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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