74LVC3G06GT,115

74LVC3G06 Triple inverter with open-drain output Rev. 15 20 April 2021 Product data sheet 1. General description The 74LVC3G06 is a triple inverter with open-drain outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V -24 mA output drive (V = 3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74LVC3G06 Triple inverter with open-drain output 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC3G06DP -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74LVC3G06DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74LVC3G06GT -40 C to +125 C XSON8 plastic extremely thin small outline package SOT833-1 no leads 8 terminals body 1 1.95 0.5 mm 74LVC3G06GN -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74LVC3G06GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes Type number Marking code 1 74LVC3G06DP V06 74LVC3G06DC V06 74LVC3G06GT V06 74LVC3G06GN V6 74LVC3G06GS V6 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 1 2A 2Y Y 3A 3Y 1 A 001aah899 001aah900 GND mna586 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one inverter) 74LVC3G06 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 15 20 April 2021 2 / 15