Product Information

74LVC273PW,118

74LVC273PW,118 electronic component of Nexperia

Datasheet
Flip Flops 3.3V OCTAL POS D-TYPE
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

2500: USD 0.1664 ea
Line Total: USD 416

16975 - Global Stock
Ships to you between
Mon. 06 May to Fri. 10 May
MOQ: 2500  Multiples: 2500
Pack Size: 2500

 More Buying Options & Price Grid(s)

Availability Price Quantity
2425 - Warehouse 1


Ships to you between Mon. 06 May to Fri. 10 May

MOQ : 5000
Multiples : 2500

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74LVC273PW,118
Nexperia

5000 : USD 0.1971

12960 - Warehouse 2


Ships to you between Fri. 10 May to Tue. 14 May

MOQ : 1
Multiples : 1

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74LVC273PW,118
Nexperia

1 : USD 0.4761
10 : USD 0.3887
100 : USD 0.3036
500 : USD 0.2668
1000 : USD 0.2185
2500 : USD 0.1909
10000 : USD 0.1817

16975 - Warehouse 3


Ships to you between Mon. 06 May to Fri. 10 May

MOQ : 2500
Multiples : 2500

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74LVC273PW,118
Nexperia

2500 : USD 0.1664

45 - Warehouse 4


Ships to you between Mon. 06 May to Fri. 10 May

MOQ : 38
Multiples : 1

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74LVC273PW,118
Nexperia

38 : USD 0.1918

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Family
Logic Type
Polarity
Input Type
Propagation Delay Time
High Level Output Current
Supply Voltage - Min
Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Brand
Number Of Input Lines
Number Of Output Lines
Factory Pack Quantity :
Height
Length
Quiescent Current
Width
Cnhts
Hts Code
Mxhts
Operating Supply Voltage
Product Type
Reset Type
Subcategory
Taric
Category
Brand Category
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Additional Infomation About Product

74LVC273 Octal D-type flip-flop with reset positive-edge trigger Rev. 8 31 August 2021 Product data sheet 1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power consumption Direct interface with TTL levels Output drive capability 50 transmission lines at +85 C Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC273D -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVC273PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVC273BQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mmNexperia 74LVC273 Octal D-type flip-flop with reset positive-edge trigger 4. Functional diagram 11 CP C1 1 R MR 11 3 2 1D CP D0 Q0 3 2 D0 Q0 4 5 D1 Q1 4 5 D1 Q1 7 6 7 6 D2 Q2 D2 Q2 8 9 8 9 D3 Q3 D3 Q3 13 12 13 12 D4 Q4 D4 Q4 14 15 14 15 D5 Q5 D5 Q5 17 16 D6 Q6 17 16 D6 Q6 18 19 D7 Q7 18 19 MR D7 Q7 1 mna763 mna764 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 5. Pinning information 5.1. Pinning 74LVC273 terminal 1 index area 2 19 Q0 Q7 D0 3 18 D7 D1 4 17 D6 74LVC273 Q1 5 16 Q6 1 20 MR V Q2 6 15 Q5 CC 2 19 Q0 Q7 7 14 D2 D5 3 18 D0 D7 D3 8 (1) 13 D4 GND 4 17 D1 D6 Q3 9 12 Q4 5 16 Q1 Q6 6 15 Q2 Q5 7 14 001aad094 D2 D5 8 13 D3 D4 Transparent top view 9 12 Q3 Q4 (1) This is not a ground pin. There is no electrical or 10 11 GND CP mechanical requirement to solder the pad. In case 001aad093 soldered, the solder land should remain floating or connected to GND. Fig. 3. Pin configuration for SOT163-1 (SO20) and SOT360-1 (TSSOP20) Fig. 4. Pin configuration for SOT764-1 (DHVQFN20) 74LVC273 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 31 August 2021 2 / 14 GND 10 1 MR CP 11 20 V CC

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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