74LVC1G38GX,125

74LVC1G38 2-input NAND gate open drain Rev. 7 4 October 2012 Product data sheet 1. General description The 74LVC1G38 provides a 2-input NAND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7(1.65 Vto1.95V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (V =3.0 V) CC CMOS low power consumption Open drain outputs Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 C to +125 C.74LVC1G38 NXP Semiconductors 2-input NAND gate open drain 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G38GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74LVC1G38GV 40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74LVC1G38GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74LVC1G38GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74LVC1G38GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74LVC1G38GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 74LVC1G38GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin SOT1226 small outline package no leads 5 terminals body 0.8 0.8 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74LVC1G38GW YB 74LVC1G38GV YB 74LVC1G38GM YB 74LVC1G38GF YB 74LVC1G38GN YB 74LVC1G38GS YB 74LVC1G38GX YB 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y A 1 A 1 & Y 4 4 2 B 2 B GND 001aab716 001aab717 001aab715 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74LVC1G38 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 4 October 2012 2 of 19