Product Information

74LVC138APW,118

74LVC138APW,118 electronic component of Nexperia

Datasheet
Encoders, Decoders, Multiplexers & Demultiplexers 3TO8 LINE DECDR DEMULPLXR IN

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

2500: USD 0.105 ea
Line Total: USD 262.5

2425 - Global Stock
Ships to you between
Wed. 08 May to Tue. 14 May
MOQ: 2500  Multiples: 2500
Pack Size: 2500
Availability Price Quantity
679 - WHS 1


Ships to you between Wed. 08 May to Tue. 14 May

MOQ : 1
Multiples : 1
1 : USD 0.2412
10 : USD 0.2389
25 : USD 0.1503
100 : USD 0.1472
250 : USD 0.1472
500 : USD 0.1472

2425 - WHS 2


Ships to you between Wed. 08 May to Tue. 14 May

MOQ : 2500
Multiples : 2500
2500 : USD 0.105
5000 : USD 0.105
10000 : USD 0.105

213 - WHS 3


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MOQ : 81
Multiples : 1
81 : USD 0.403
250 : USD 0.351
1250 : USD 0.2925

965 - WHS 4


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MOQ : 5
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5 : USD 0.3363
50 : USD 0.2716
150 : USD 0.2439
500 : USD 0.2094
2500 : USD 0.194
5000 : USD 0.1847

16053 - WHS 5


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MOQ : 1
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1 : USD 0.3979
10 : USD 0.3036
100 : USD 0.1898
1000 : USD 0.1587
2500 : USD 0.1254
10000 : USD 0.1196
25000 : USD 0.1173

1647 - WHS 6


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MOQ : 1
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1 : USD 0.481
3 : USD 0.4329
10 : USD 0.403
25 : USD 0.3588
78 : USD 0.2093

4850 - WHS 7


Ships to you between Wed. 08 May to Tue. 14 May

MOQ : 2500
Multiples : 2500
2500 : USD 0.1113

679 - WHS 8


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MOQ : 62
Multiples : 1
62 : USD 0.1503
100 : USD 0.1472

2425 - WHS 9


Ships to you between Wed. 08 May to Tue. 14 May

MOQ : 2500
Multiples : 2500
2500 : USD 0.105

     
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RoHS - XON
Icon ROHS
Logic Family
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Supply Voltage - Max
Supply Voltage - Min
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74LVC138A 3-to-8 line decoder/demultiplexer inverting Rev. 8 20 September 2021 Product data sheet 1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74LVC138A to a 1-of-32 (5 to 32 lines) decoder with just four 74LVC138A ICs and one inverter. The 74LVC138A can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. 2. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Mutually exclusive outputs Output drive capability 50 transmission lines at 125 C Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC138AD -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LVC138APW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74LVC138ABQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mmNexperia 74LVC138A 3-to-8 line decoder/demultiplexer inverting 4. Functional diagram DX 15 X/Y 15 0 0 1 1 14 14 0 1 1 1 2 13 2 13 0 G 2 1 A0 Y0 15 2 2 7 3 12 3 12 Y1 14 2 A1 2 3 4 3 11 11 3 A2 Y2 13 4 4 Y3 12 10 10 4 4 & & 5 5 11 E1 Y4 4 9 9 5 5 6 6 10 Y5 E2 EN 5 7 7 6 6 7 7 Y6 9 E3 6 7 Y7 mna371 mna370 (a) (b) Fig. 1. Logic symbol Fig. 2. IEC logic symbol Y0 15 1 A0 Y1 14 A1 2 Y2 13 A2 3 Y3 12 3-to-8 ENABLE Y4 11 DECODER EXITING Y5 10 Y6 9 Y7 7 4 E1 5 E2 6 E3 mna372 Fig. 3. Functional diagram 5. Pinning information 5.1. Pinning 74LVC138A A0 1 16 V CC 74LVC138A A1 2 15 Y0 A2 3 14 Y1 A0 1 16 V CC A1 2 15 Y0 4 13 E1 Y2 A2 3 14 Y1 E2 5 12 Y3 E1 4 13 Y2 E2 5 12 Y3 E3 6 11 Y4 E3 6 11 Y4 Y7 7 10 Y5 Y7 7 10 Y5 GND 8 9 Y6 GND 8 9 Y6 001aad033 aaa-029538 Fig. 4. Pin configuration SOT109-1 (SO16) Fig. 5. Pin configuration SOT403-1 (TSSOP16) 74LVC138A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 20 September 2021 2 / 14

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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