74LV138DB,118

74LV138 3-to-8 line decoder/demultiplexer inverting Rev. 6 22 July 2021 Product data sheet 1. General description The 74LV138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (Y1, Y2 and E3). Every output will be HIGH unless Y1 and Y2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74LV138 to a 1-of-32 (5 to 32 lines) decoder with just four 74LV138 ICs and one inverter. The 74LV138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Wide supply voltage range from 1.0 to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V CMOS low power dissipation Direct interface with TTL levels Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and T = 25 C OH CC amb Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Active LOW mutually exclusive outputs Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 CNexperia 74LV138 3-to-8 line decoder/demultiplexer inverting 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV138D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LV138PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74LV138BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 4. Functional diagram DX 15 X/Y 15 0 0 1 14 1 14 0 1 1 1 2 0 13 2 13 G 2 Y0 2 2 1 A0 15 7 3 12 3 12 2 A1 Y1 14 2 3 4 3 11 11 3 A2 13 Y2 4 4 12 Y3 10 10 4 4 & & 5 5 E1 Y4 11 9 9 4 5 5 6 6 Y5 10 E2 EN 5 7 7 6 6 9 7 7 Y6 E3 6 7 Y7 mna371 (a) (b) mna370 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Y0 15 A0 Y1 1 14 2 A1 Y2 13 3 A2 Y3 12 3-to-8 ENABLE Y4 11 DECODER EXITING Y5 10 Y6 9 7 Y7 4 E1 5 E2 6 E3 mna372 Fig. 3. Functional diagram 74LV138 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 22 July 2021 2 / 14