Product Information

74LV08DB,112

74LV08DB,112 electronic component of Nexperia

Datasheet
Logic Gates QUAD 2-INPUT AND

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - WHS 1

MOQ : 1092
Multiples : 1

Stock Image

74LV08DB,112
Nexperia

1092 : USD 0.2894
N/A

Obsolete
0 - WHS 2

MOQ : 1
Multiples : 1

Stock Image

74LV08DB,112
Nexperia

1 : USD 1.4209
10 : USD 0.642
100 : USD 0.3222
1000 : USD 0.2677
2500 : USD 0.2436
10000 : USD 0.2398
25000 : USD 0.236
50000 : USD 0.2309
100000 : USD 0.222
N/A

Obsolete
     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Product
Logic Function
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Brand
Number Of Lines In/Out
Factory Pack Quantity :
Function
Height
Length
Width
Logic Type
Cnhts
Hts Code
Mxhts
Operating Supply Voltage
Product Type
Subcategory
Taric
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74LV08 Quad 2-input AND gate Rev. 5 13 September 2021 Product data sheet 1. General description The 74LV08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Wide supply voltage range from 1.0 to 5.5 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and T = 25 C OH CC amb Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV08D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV08PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mmNexperia 74LV08 Quad 2-input AND gate 4. Functional diagram 1 & 3 2 4 & 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B & 8 10 9 3A 3Y 8 10 3B A 12 12 4A & 11 4Y 11 Y 13 4B 13 B mna222 mna223 mna221 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74LV08 74LV08 1A 1 14 V CC 1B 2 13 4B 1A 1 14 V CC 1Y 3 12 4A 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2A 4 11 4Y 5 10 2B 3B 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y GND 7 8 3Y 001aaj959 001aaj960 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74LV08 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 13 September 2021 2 / 11

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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