Product Information

74HCT74D

74HCT74D electronic component of Nexperia

Datasheet
74 Series SOIC-14_150mil RoHS

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

5: USD 0.4516 ea
Line Total: USD 2.26

0 - Global Stock
MOQ: 5  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 10 May to Thu. 16 May

MOQ : 5
Multiples : 1

Stock Image

74HCT74D
Nexperia

5 : USD 0.4448
50 : USD 0.3374
100 : USD 0.2465
500 : USD 0.2105
1000 : USD 0.1744

0 - WHS 2


Ships to you between
Fri. 17 May to Wed. 22 May

MOQ : 1
Multiples : 1

Stock Image

74HCT74D
Nexperia

1 : USD 0.2623
10 : USD 0.2146
30 : USD 0.1802
100 : USD 0.1518
500 : USD 0.1467
1000 : USD 0.1445

     
Manufacturer
Product Category
Packaging
Brand
Logic Family / Base Number
Flip-Flop Type
Propagation Delay
Frequency
Output Current
Logic Case Style
No. Of Pins
Trigger Type
Ic Output Type
Supply Voltage Min
Supply Voltage Max
Logic Ic Family
Logic Ic Base Number
Operating Temperature Min
Operating Temperature Max
Rohs Phthalates Compliant
Msl
Svhc
Base Number
Ic Generic Number
Logic Function Number
Logic Ic Function
No. Of Gates
Operating Temperature Range
Supply Voltage
Supply Voltage Range
Termination Type
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INTEGRATED CIRCUITS DATA SHEET 74HC74 74HCT74 Dual D-type flip-flop with set and reset positive-edge trigger Product specication 2003 Jul 10 Supersedes data of 1998 Feb 23Philips Semiconductors Product specication Dual D-type ip-op with set and reset 74HC74 74HCT74 positive-edge trigger FEATURES GENERAL DESCRIPTION Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL Symmetrical output impedance (LSTTL). They are specified in compliance with JEDEC High noise immunity standard no. 7A. Low power dissipation The 74HC/HCT74 are dual positive-edge triggered, D-type Balanced propagation delays flip-flops with individual data (D) inputs, clock (CP) inputs, ESD protection: set (SD) and reset (RD) inputs also complementary HBM EIA/JESD22-A114-A exceeds 2000 V Q and Q outputs. MM EIA/JESD22-A115-A exceeds 200 V. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V T =25 C t =t =6ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t /t propagation delay C = 15 pF V =5V PHL PLH L CC nCP to nQ, nQ1415ns nSD to nQ, nQ1518ns nRD to nQ, nQ1618ns f maximum clock frequency 76 59 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per ip-op notes 1 and 2 24 29 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in Volts CC N = total load switching outputs 2 (C V f ) = sum of the outputs. L CC o 2. For 74HC74 the condition is V = GND to V . I CC For 74HCT74 the condition is V = GND to V - 1.5 V. I CC 2003 Jul 10 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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