Product Information

74HC73PW,112

74HC73PW,112 electronic component of Nexperia

Datasheet
Flip Flops DUAL J-K MASTR-SLAVE

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - Warehouse 1

MOQ : 96
Multiples : 1

Stock Image

74HC73PW,112
Nexperia

96 : USD 0.2653
100 : USD 0.2477
200 : USD 0.2407
480 : USD 0.2337
960 : USD 0.2267
4800 : USD 0.2197
9600 : USD 0.2128
N/A

Obsolete
0 - Warehouse 2

MOQ : 1
Multiples : 1

Stock Image

74HC73PW,112
Nexperia

1 : USD 0.6409
10 : USD 0.5528
96 : USD 0.428
576 : USD 0.3478
1056 : USD 0.2898
2592 : USD 0.2664
5088 : USD 0.2553
10080 : USD 0.2553
25056 : USD 0.2475
N/A

Obsolete
     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Family
Logic Type
Polarity
Input Type
Output Type
Propagation Delay Time
High Level Output Current
Low Level Output Current
Supply Voltage - Min
Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Function
Height
Length
Quiescent Current
Width
Brand
Number Of Channels
Number Of Input Lines
Number Of Output Lines
Operating Supply Voltage
Reset Type
Factory Pack Quantity :
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74HC73 Dual JK flip-flop with reset negative-edge trigger Rev. 7 13 September 2021 Product data sheet 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits CMOS low-power dissipation Wide supply voltage range from 2.0 to 6.0 V High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +80 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC73D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HC73PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mmNexperia 74HC73 Dual JK flip-flop with reset negative-edge trigger 4. Functional diagram 14 1J 1Q 12 J Q FF1 1 1CP CP 3 1K 1Q 13 K Q R 2 1R 14 1J 12 1 C1 3 7 2J 2Q 9 14 1J 1Q 12 1K J Q J Q 13 7 2J 2Q 9 2 R FF2 FF 1 1CP 5 2CP CP CP 5 2CP 7 1J 3 1K 1Q 13 9 10 2K 2Q 8 K Q 5 K Q 10 2K 2Q 8 C1 10 R R 1K 8 6 6 2R R 1R 2R 2 6 001aab981 001aab979 001aab980 Fig. 1. Functional diagram Fig. 2. Logic symbol Fig. 3. IEC logic symbol C C C C K Q J C C C C R Q C CP 001aab982 C Fig. 4. Logic diagram (one flip-flop) 74HC73 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 7 13 September 2021 2 / 13

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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