Product Information

74HC4075PW-Q100J

74HC4075PW-Q100J electronic component of Nexperia

Datasheet
Logic Gates Triple 3-input OR gate

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 1.0267 ea
Line Total: USD 1.03

1242 - Global Stock
Ships to you between
Thu. 09 May to Mon. 13 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2143 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1
1 : USD 0.5739
10 : USD 0.5048
100 : USD 0.3922
500 : USD 0.3185
1000 : USD 0.2657
2500 : USD 0.2449
5000 : USD 0.2346
10000 : USD 0.2346
25000 : USD 0.2265

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Product
Logic Function
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Operating Temperature Range
Output Current
Output Voltage
Brand
Pd - Power Dissipation
Product Type
Factory Pack Quantity :
Subcategory
Cnhts
Hts Code
Mxhts
Taric
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74HC4075-Q100 74HCT4075-Q100 Triple 3-input OR gate Rev. 2 4 February 2019 Product data sheet 1. General description The 74HC4075-Q100 74HCT4075-Q100 is a triple 3-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Complies with JEDEC standard JESD7A Input levels: For 74HC4075-Q100: CMOS level For 74HCT4075-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4075D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT4075D-Q100 74HC4075PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mmNexperia 74HC4075-Q100 74HCT4075-Q100 Triple 3-input OR gate 4. Functional diagram 3 1A 6 4 1Y 1B 3 1 5 1C 4 6 5 1 2A 2Y 9 1 2 2B 1 2 9 8 2C 8 A 11 3A 11 1 10 12 3B 3Y B Y 12 10 13 3C 13 C aaa-024793 aaa-024794 aaa-024795 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74HC4075-Q100 74HCT4075-Q100 2A 1 14 V CC 74HC4075-Q100 2B 2 13 3C 2A 1 14 V 1A 3 12 3B CC 2B 2 13 3C 3A 1B 4 11 1A 3 12 3B 1C 5 10 3Y 1B 4 11 3A 1C 5 10 3Y 1Y 6 9 2Y 1Y 6 9 2Y GND 7 8 2C GND 7 8 2C aaa-007623 aaa-007624 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A 3, 1, 11 data input 1B, 2B, 3B 4, 2, 12 data input 1C, 2C, 3C 5, 8, 13 data input 1Y, 2Y, 3Y 6, 9, 10 data output GND 7 ground (0 V) V 14 supply voltage CC 74HC HCT4075 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 2 4 February 2019 2 / 12

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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