Product Information

74HC273D-Q100J

74HC273D-Q100J electronic component of Nexperia

Datasheet
NXP Semiconductors Flip Flops Octal Dtype flipflop positive edgetrigger
Manufacturer: Nexperia
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Price (USD)

1: USD 1.2634 ea
Line Total: USD 1.26

1872 - Global Stock
Ships to you between
Thu. 16 May to Mon. 20 May
MOQ: 1  Multiples: 1
Pack Size: 1

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1625 - WHS 1


Ships to you between Thu. 16 May to Mon. 20 May

MOQ : 1
Multiples : 1

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74HC273D-Q100J
Nexperia

1 : USD 0.6992
10 : USD 0.5911
100 : USD 0.4554
500 : USD 0.3841
1000 : USD 0.3163
2000 : USD 0.2714
4000 : USD 0.2611
10000 : USD 0.2553
24000 : USD 0.2541

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Additional Infomation About Product

74HC273-Q100 74HCT273-Q100 Octal D-type flip-flop with reset positive-edge trigger Rev. 2 3 September 2020 Product data sheet 1. General description The 74HC273-Q100 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC273-Q100: CMOS level For 74HCT273-Q100: TTL level Common clock and master reset Eight positive edge-triggered D-type flip-flops ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder jointsNexperia 74HC273-Q100 74HCT273-Q100 Octal D-type flip-flop with reset positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74HC273D-Q100 -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74HCT273D-Q100 74HC273PW-Q100 -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74HCT273PW-Q100 74HC273BQ-Q100 -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals 74HCT273BQ-Q100 body 2.5 4.5 0.85 mm 4. Functional diagram 11 CP C1 1 R MR 11 3 2 1D CP D0 Q0 D0 Q0 3 2 3 2 D0 Q0 D1 Q1 4 5 4 5 D1 Q1 4 5 D2 Q2 D1 Q1 7 6 7 6 7 6 D2 Q2 D3 Q3 FF1 D2 Q2 8 9 D4 TO Q4 8 9 8 9 D3 Q3 13 12 D3 Q3 FF8 D5 Q5 13 12 14 15 13 12 D4 Q4 D4 Q4 D6 Q6 17 16 14 15 14 15 D5 Q5 D7 Q7 D5 Q5 18 19 17 16 D6 Q6 17 16 MR D6 Q6 18 19 1 D7 Q7 CP 18 19 MR 11 D7 Q7 1 001aae055 mna763 mna764 Fig. 1. Functional diagram Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74HC HCT273 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 3 September 2020 2 / 18

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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