Product Information

74HC11D-Q100J

74HC11D-Q100J electronic component of Nexperia

Datasheet
NXP Semiconductors Logic Gates

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

5: USD 0.2506 ea
Line Total: USD 1.25

2255 - Global Stock
Ships to you between
Fri. 17 May to Wed. 22 May
MOQ: 5  Multiples: 5
Pack Size: 5
Availability Price Quantity
2255 - WHS 1


Ships to you between
Fri. 17 May to Wed. 22 May

MOQ : 5
Multiples : 5

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74HC11D-Q100J
Nexperia

5 : USD 0.2506
50 : USD 0.219
150 : USD 0.2054
500 : USD 0.1887
2500 : USD 0.1812
5000 : USD 0.1767

693 - WHS 2


Ships to you between Thu. 16 May to Mon. 20 May

MOQ : 1
Multiples : 1

Stock Image

74HC11D-Q100J
Nexperia

1 : USD 0.5739
10 : USD 0.475
100 : USD 0.3599
500 : USD 0.2921
1000 : USD 0.2311
2500 : USD 0.1944
10000 : USD 0.1944
25000 : USD 0.1886
50000 : USD 0.1874

     
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RoHS - XON
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74HC11-Q100 74HCT11-Q100 Triple 3-input AND gate Rev. 4 11 August 2021 Product data sheet 1. General description The 74HC11-Q100 74HCT11-Q100 is a triple 3-input AND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: For 74HC11-Q100: CMOS level For 74HCT11-Q100: TTL level Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC11D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT11D-Q100 74HC11PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package SOT402-1 14 leads body width 4.4 mm 74HCT11PW-Q100Nexperia 74HC11-Q100 74HCT11-Q100 Triple 3-input AND gate 4. Functional diagram 1 & 12 2 1 1A 13 1Y 12 2 1B 13 1C 3 3 2A & 6 4 4 2B 2Y 6 5 5 2C A 9 3A 9 10 3Y 8 3B & Y B 10 8 11 3C 11 C mna794 mna793 mna792 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram for one gate 5. Pinning information 5.1. Pinning 74HC11 74HCT11 74HC11 74HCT11 1A 1 14 V CC 1B 2 13 1C 1A 1 14 V CC 3 12 2A 1Y 1B 2 13 1C 2A 3 12 1Y 2B 4 11 3C 2B 4 11 3C 2C 5 10 3B 2C 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y GND 7 8 3Y 001aal407 001aal408 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A 1, 3, 9 data input 1B, 2B, 3B 2, 4, 10 data input GND 7 ground (0 V) 1C, 2C, 3C 13, 5, 11 data input 1Y, 2Y, 3Y 12, 6, 8 data output V 14 supply voltage CC 74HC HCT11 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 11 August 2021 2 / 11

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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