74CBTLVD3245-Q100 8-bit level-shifting bus switch with output enable Rev. 5 4 February 2021 Product data sheet 1. General description The 74CBTLVD3245-Q100 is an 8-pole, single-throw bus switch. The device features a single output enable input (OE) that controls eight switch channels. The switches are disabled when OE is HIGH. Schmitt trigger action at control inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Supply voltage range from 3.0 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-B/JESD36 (3.0 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V CDM AEC-Q100-011 revision B exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A I circuitry provides partial Power-down mode operation OFF DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLVD3245BQ-Q100 -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal SOT764-1 enhanced very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mmNexperia 74CBTLVD3245-Q100 8-bit level-shifting bus switch with output enable 4. Functional diagram A1 A2 A3 A4 A5 A6 A7 A8 2 18 A1 B1 2 3 4 5 6 7 8 9 19 OE 9 11 18 17 16 15 14 13 12 11 B8 A8 19 B1 B2 B3 B4 B5 B6 B7 B8 OE 001aao116 001aao117 Fig. 1. Logic symbol Fig. 2. Logic diagram 5. Pinning information 5.1. Pinning 74CBTLVD3245-Q100 terminal 1 index area A1 2 19 OE A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 6 15 A5 B4 A6 7 14 B5 (1) A7 8 13 B6 GND A8 9 12 B7 aaa-020101 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Fig. 3. Pin configuration SOT764-1 (DHVQFN20) 5.2. Pin description Table 2. Pin description Symbol Pin Description n.c. 1 not connected A1 to A8 2, 3, 4, 5, 6, 7, 8, 9 data input/output (A port) GND 10 ground (0 V) B1 to B8 18, 17, 16, 15, 14, 13, 12, 11 data input/output (B port) OE 19 output enable input (active LOW) V 20 positive supply voltage CC 74CBTLVD3245 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 4 February 2021 2 / 13 GND 10 1 n.c. 11 20 B8 V CC