74CBTLV3306GTX

74CBTLV3306 2-bit bus switch Rev. 1 7 December 2016 Product data sheet 1. General description The 74CBTLV3306 is a 2-bit high-speed bus switch with separate output enable inputs (nOE). Each switch is disabled when the associated output enable (nOE) input is HIGH. To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to the V through a pull-up resistor. The minimum value of the resistor is determined CC by the current-sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire V range from 2.3 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V 4 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74CBTLV3306 Nexperia 2-bit bus switch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLV3306DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74CBTLV3306GT 40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mm 4. Marking Table 2. Marking codes 1 Type number Marking code 74CBTLV3306DC b6 74CBTLV3306GT b6 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram ( Q Q% ( Q2( DDD DN D Fig 1. Logic symbol Fig 2. Logic diagram (one switch) 74CBTLV3306 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 1 7 December 2016 2 of 17 % 2 % 2