Product Information

74CBTLV1G125GV,125

74CBTLV1G125GV,125 electronic component of Nexperia

Datasheet
Digital Bus Switch ICs LV BUFFER/LINE DRV

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.437 ea
Line Total: USD 0.44

4557 - Global Stock
Ships to you between
Thu. 09 May to Mon. 13 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
4557 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1
1 : USD 0.437
10 : USD 0.3485
100 : USD 0.1966
1000 : USD 0.1414
3000 : USD 0.123
24000 : USD 0.1173
45000 : USD 0.1127
99000 : USD 0.1092

     
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RoHS - XON
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74CBTLV1G125 Single bus switch Rev. 4 5 September 2012 Product data sheet 1. General description The 74CBTLV1G125 provides a single high-speed line switch. The switch is disabled when the output enable (OE) input is high. To ensure the high-impedance OFF-state during power-up or power-down, tie OE to the V through a pull-up resistor. The current-sinking capability of the driver determines the CC minimum value of the resistor. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire V range from 2.3 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance meets requirements of JESD78 Class I I circuitry provides partial power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74CBTLV1G125 NXP Semiconductors Single bus switch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLV1G125GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74CBTLV1G125GV 40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74CBTLV1G125GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74CBTLV1G125GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74CBTLV1G125GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74CBTLV1G125GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74CBTLV1G125GW bM 74CBTLV1G125GV b25 74CBTLV1G125GM bM 74CBTLV1G125GF bM 74CBTLV1G125GN bM 74CBTLV1G125GS bM 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram AB 2 4 A SWITCH B OE 1 OE 001aad713 001aad714 Fig 1. Logic symbol Fig 2. Logic diagram 74CBTLV1G125 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 5 September 2012 2 of 21

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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