Product Information

74AVCH1T45GW

74AVCH1T45GW electronic component of Nexperia

Datasheet
IC, TXRX, DUAL SUPPLY, 3-ST, SC-88
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

5: USD 0.5805 ea
Line Total: USD 2.9

0 - Global Stock
MOQ: 5  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 10 May to Thu. 16 May

MOQ : 5
Multiples : 1

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74AVCH1T45GW
Nexperia

5 : USD 0.4768
10 : USD 0.3749
100 : USD 0.3027
500 : USD 0.2674
1000 : USD 0.1823
5000 : USD 0.1728

Read More Specifications

     
Manufacturer
Product Category
Logic Device Type
Logic Case Style
No Of Pins
Supply Voltage Min
Supply Voltage Max
Operating Temperature Min
Operating Temperature Max
Packaging
Msl
Svhc
Data Rate
Operating Temperature Range
Supply Voltage Range
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Additional Infomation About Product

74AVCH1T45 Dual-supply voltage level translator/transceiver 3-state Rev. 5 6 January 2016 Product data sheet 1. General description The 74AVCH1T45 is a single bit, dual supply transceiver that enables bidirectional level translation. It features two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (V and V ). Both V and V can be supplied at any CC(A) CC(B) CC(A) CC(B) voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to V and pin B is referenced to V . A HIGH on DIR allows CC(A) CC(B) transmission from A to B and a LOW on DIR allows transmission from B to A. The device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at CC(A) CC(B) GND level, both A and B are in the high-impedance OFF-state. The 74AVCH1T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features and benefits Wide supply voltage range: V : 0.8 V to 3.6 V CC(A) V : 0.8 V to 3.6 V CC(B) High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Maximum data rates: 500 Mbit/s (1.8 V to 3.3 V translation) 320 Mbit/s (< 1.8 V to 3.3 V translation) 320 Mbit/s (translate to 2.5 V or 1.8 V) 280 Mbit/s (translate to 1.5 V)74AVCH1T45 NXP Semiconductors Dual-supply voltage level translator/transceiver 3-state 240 Mbit/s (translate to 1.2 V) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVCH1T45GW 40 Cto +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AVCH1T45GM 40 Cto +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AVCH1T45GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AVCH1T45GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74AVCH1T45GW K5 74AVCH1T45GM K5 74AVCH1T45GN K5 74AVCH1T45GS K5 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74AVCH1T45 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 5 6 January 2016 2 of 24

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