74AVC1T8128GSX

74AVC1T8128 Single dual-supply translating 2-input NOR with enable Rev. 1 10 October 2018 Product data sheet 1. General description The 74AVC1T8128 is a single dual-supply translating 2-input NOR with enable input. It features two data input pins (A, B), one enable input pin (E), one data output pin (Y) and dual-supply pins (V and V ). Both V and V can be supplied at any voltage between 0.8 V and CC(A) CC(B) CC(A) CC(B) 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A, B and E are referenced to V and pin Y is referenced to CC(A) V . CC(B) The logic equation provided at the Y output is: Y = E + AB The device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing any damaging backflow current through the device when it is powered down. In Suspend mode when either V or V are at GND level, the Y output is in CC(A) CC(B) the high-impedance OFF-state. 2. Features and benefits Wide supply voltage range: V : 0.8 V to 3.6 V CC(A) V : 0.8 V to 3.6 V CC(B) High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 exceeds 8000 V CDM: ANSI/ESDA/JEDEC JS-002 exceeds 1000 V Maximum data rates: 500 Mbit/s (1.8 V to 3.3 V translation) 320 Mbit/s (<1.8 V to 3.3 V translation) 320 Mbit/s (translate to 2.5 V or 1.8 V) 280 Mbit/s (translate to 1.5 V) 240 Mbit/s (translate to 1.2 V) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AVC1T8128 Single dual-supply translating 2-input NOR with enable 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC1T8128GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 x 1.0 x 0.35 mm 4. Marking Table 2. Marking Type number Marking code 1 74AVC1T8128GS Be 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 5 7 E Y 3 B 2 A V V CC(A) CC(B) aaa-029170 Fig. 1. Logic symbol 6. Pinning information 6.1. Pinning 74AVC1T8128 V 1 8 V CC(A) CC(B) A 2 7 Y B 3 6 n.c. GND 4 5 E aaa-029171 Transparent top view Fig. 2. Pin configuration SOT1203 (XSON8) 74AVC1T8128 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 1 10 October 2018 2 / 12