74AUP3G04GT,115

74AUP3G04 Low-power triple inverter Rev. 10 15 December 2020 Product data sheet 1. General description The 74AUP3G04 provides a low-power, low-voltage triple inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using I . The I circuitry OFF OFF disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AUP3G04 Low-power triple inverter 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP3G04DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74AUP3G04GT -40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 1.95 0.5 mm 74AUP3G04GN -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74AUP3G04GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes Type number Marking code 1 74AUP3G04DC p04 74AUP3G04GT p04 74AUP3G04GN p4 74AUP3G04GS p4 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 1 2A 2Y 1 3A 3Y A Y 001aah793 001aah794 mna110 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 74AUP3G04 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 10 15 December 2020 2 / 17