Product Information

74AUP2G34GW

74AUP2G34GW electronic component of Nexperia

Datasheet
IC, DUAL, BUFFER, NON INV, SC-88
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

5: USD 0.6447 ea
Line Total: USD 3.22

0 - Global Stock
MOQ: 5  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 10 May to Thu. 16 May

MOQ : 5
Multiples : 1

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74AUP2G34GW
Nexperia

5 : USD 0.6447
10 : USD 0.4317
100 : USD 0.1806
500 : USD 0.1668
1000 : USD 0.1522
5000 : USD 0.1423

Read More Specifications

     
Manufacturer
Product Category
Logic Device Type
Logic Case Style
No Of Pins
Supply Voltage Min
Supply Voltage Max
Operating Temperature Min
Operating Temperature Max
Packaging
Msl
Svhc
Operating Temperature Range
Supply Voltage Range
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Additional Infomation About Product

74AUP2G34 Low-power dual buffer Rev. 6 17 September 2015 Product data sheet 1. General description The 74AUP2G34 provides two low-power, low-voltage buffers. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP2G34 NXP Semiconductors Low-power dual buffer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G34GW 40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP2G34GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP2G34GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74AUP2G34GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP2G34GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 74AUP2G34GX 40 C to +125 C X2SON6 plastic thermal extremely thin small outline package SOT1255 no leads 6 terminals body 1 0.8 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74AUP2G34GW aA 74AUP2G34GM aA 74AUP2G34GF aA 74AUP2G34GN aA 74AUP2G34GS aA 74AUP2G34GX aA 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram < < < PQ QE P DF D Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74AUP2G34 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 17 September 2015 2 of 20 E

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