74AUP1T50GWH

74AUP1T50 Low-power buffer with voltage-level translator Rev. 2 19 July 2021 Product data sheet 1. General description The 74AUP1T50 provides the single buffer function. This device ensures a very low static and dynamic power consumption across the entire V range from 2.3 V to 3.6 V. CC The 74AUP1T50 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire V range. CC 2. Features and benefits Wide supply voltage range from 2.3 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 1.5 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1T50GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74AUP1T50GX -40 C to +125 C X2SON5 plastic thermal enhanced extremely thin SOT1226-3 small outline package no leads 5 terminals body 0.8 0.8 0.32 mmNexperia 74AUP1T50 Low-power buffer with voltage-level translator 4. Marking Table 2. Marking Type number Marking code 1 74AUP1T50GW 5E 74AUP1T50GX 5E 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A Y 2 4 2 4 A Y mnb150 mnb151 mnb152 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1T50 74AUP1T50 n.c. 1 5 V CC n.c. 1 5 V CC 3 GND A 2 A 2 4 Y GND 3 4 Y aaa-027774 aaa-027773 Transparent top view Fig. 4. Pin configuration SOT353-1 (TSSOP5) Fig. 5. Pin configuration SOT1226-3 (X2SON5) 6.2. Pin description Table 3. Pin description Symbol Pin Description n.c. 1 not connected A 2 data input GND 3 ground (0 V) Y 4 data output V 5 supply voltage CC 74AUP1T50 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 2 19 July 2021 2 / 14