74ALVC373PW,118

74ALVC373 Octal D-type transparent latch 3-state Rev. 3 30 April 2021 Product data sheet 1. General description The 74ALVC373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. This device is fully specified for partial power down applications using I . The I OFF OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC373D -40 C to +85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74ALVC373PW -40 C to +85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74ALVC373BQ -40 C to +85 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mmNexperia 74ALVC373 Octal D-type transparent latch 3-state 4. Functional diagram 1 EN 11 D7 Q7 18 19 C1 D6 Q6 17 16 3 2 1D D5 Q5 14 15 4 5 D4 Q4 13 12 7 6 D3 Q3 8 9 8 9 D2 Q2 7 6 13 12 D1 Q1 4 5 14 15 D0 Q0 3 2 17 16 LE OE 18 19 mna881 11 1 mna880 Fig. 1. Logic symbol Fig. 2. IEC logic symbol D0 Q0 3 2 D1 Q1 4 5 D2 Q2 7 6 D3 Q3 8 9 LATCH 3-STATE D4 Q4 13 1 to 8 OUTPUTS 12 LE D5 Q5 14 15 D6 Q6 17 16 D7 Q7 18 19 LE LE 11 LE D Q 1 OE mna189 mna882 LE Fig. 3. Functional diagram Fig. 4. Logic diagram (one latch) D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna883 Fig. 5. Logic diagram 74ALVC373 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 30 April 2021 2 / 15