Product Information

NAND01GW3B2CN6E

NAND01GW3B2CN6E electronic component of Micron

Datasheet
FLASH, NAND, 1GBIT, TSOP48

Manufacturer: Micron
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 8.7672 ea
Line Total: USD 8.77

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 24 May to Thu. 30 May

MOQ : 1
Multiples : 1
1 : USD 8.7672
10 : USD 8.229
100 : USD 6.8406
250 : USD 6.1698
500 : USD 5.3898

     
Manufacturer
Product Category
Memory Size
Packaging
Memory Type
Flash Memory Configuration
Supply Voltage Min
Supply Voltage Max
Memory Case Style
No Of Pins
Clock Frequency
Access Time
Ic Interface Type
Operating Temperature Min
Operating Temperature Max
Msl
Svhc
Operating Temperature Range
Supply Voltage Range
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NAND01G-B2B NAND02G-B2C 1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory Features High density NAND flash memories Up to 2 Gbits of memory array Cost effective solutions for mass storage applications NAND interface x8 or x16 bus width TSOP48 12 x 20 mm Multiplexed address/ data Pinout compatibility for all densities FBGA Supply voltage: 1.8 V/3.0 V Page size VFBGA63 9.5 x 12 x 1 mm x8 device: (2048 + 64 spare) bytes VFBGA63 9 x 11 x 1 mm x16 device: (1024 + 32 spare) words Serial number option Block size Data protection x8 device: (128 K + 4 K spare) bytes Hardware block locking x16 device: (64 K + 2 K spare) words Hardware program/erase locked during Page read/program power transitions Random access: 25 s (max) Data integrity Sequential access: 30 ns (min) 100 000 program/erase cycles per block Page program time: 200 s (typ) (with ECC) Copy back program mode 10 years data retention Cache program and cache read modes ECOPACK packages Fast block erase: 2 ms (typ) Development tools Status register Error correction code models Electronic signature Bad blocks management and wear leveling algorithms Chip enable dont care Hardware simulation models Table 1. Device summary Reference Part number NAND01GR3B2B, NAND01GW3B2B NAND01G-B2B (1) NAND01GR4B2B, NAND01GW4B2B NAND02GR3B2C, NAND02GW3B2C NAND02G-B2C (1) NAND02GR4B2C, NAND02GW4B2C 1. x16 organization only available for MCP products. April 2008 Rev 5 1/60 www.numonyx.com 1Contents NAND01G-B2B, NAND02G-B2C Contents 1 Description . 7 2 Memory array organization 12 2.1 Bad blocks 12 3 Signals description . 14 3.1 Inputs/outputs (I/O0-I/O7) . 14 3.2 Inputs/outputs (I/O8-I/O15) 14 3.3 Address Latch Enable (AL) . 14 3.4 Command Latch Enable (CL) 14 3.5 Chip Enable (E) 14 3.6 Read Enable (R) 14 3.7 Write Enable (W) . 15 3.8 Write Protect (WP) 15 3.9 Ready/Busy (RB) . 15 3.10 V supply voltage 15 DD 3.11 V ground 15 SS 4 Bus operations 16 4.1 Command input 16 4.2 Address input 16 4.3 Data input . 16 4.4 Data output 16 4.5 Write Protect 17 4.6 Standby 17 5 Command set 19 6 Device operations 20 6.1 Read memory array . 20 6.1.1 Random read . 20 6.1.2 Page read . 20 2/60

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