N25Q128A13BSF40G

N25Q128 128-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface Additional smart protections available upon Features customer request SPI-compatible serial bus interface Electronic signature 108 MHz (maximum) clock frequency JEDEC standard two-byte signature (BA18h) 2.7 V to 3.6 V single supply voltage Additional 2 Extended Device ID (EDID) Supports legacy SPI protocol and new Quad bytes to identify device factory options I/O or Dual I/O SPI protocol Unique ID code (UID) with 14 bytes read- Quad/Dual I/O instructions resulting in an only, available upon customer request equivalent clock frequency up to 432 MHz: More than 100,000 program/erase cycles per XIP mode for all three protocols sector Configurable via volatile or non-volatile More than 20 years data retention registers: enables XiP mode directly after power on Packages (all packages RoHS compliant) F8 = VDFPN8 8 x 6 mm (MLP8) Program/Erase suspend instructions 12 = TBGA24 6 x 8 mm Continuous read (entire memory) via single F6 = VDFPN8 6 x 5 mm (MLP) instruction: SF = SO16 (300 mils body width) Fast Read SE = SO8W (SO8 208 mils body width) Quad or Dual Output Fast Read Quad or Dual I/O Fast Read Flexible to fit application: Configurable number of dummy cycles Output buffer configurable Fast POR instruction: decrease power-on time Reset function (upon customer request) 64-byte user-lockable, one-time programmable (OTP) area Erase capability Subsector (4-Kbyte) granularity in the 8 boot sectors (bottom or top parts) Sector (64-Kbyte) granularity Write protections Software write protection applicable to every 64-Kbyte sector (volatile lock bit) Hardware write protection: protected area size defined by non-volatile bits (BP0, BP1, BP2, BP3 and TB bit) July 2014 Rev 8 1/183 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved.Contents N25Q128 - 3 V Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 Serial data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 Hold (HOLD) or Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 Write protect/enhanced program supply voltage (W/VPP), DQ2 . . . . . . . 18 2.7 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CC 2.8 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SS 3 SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 Extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 Dual I/O SPI (DIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 Quad SPI (QIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Extended SPI Protocol Operating features . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.2 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.3 Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.4 Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.5 Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.6 Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.7 Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . 24 5.1.8 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 24 5.1.9 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.10 Hold (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Dual SPI (DIO-SPI) Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.1 Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/183 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved.