512Mb: x16, x32 Automotive LPDDR SDRAM Features Automotive LPDDR SDRAM MT46H32M16LF 8 Meg x 16 x 4 banks MT46H16M32LF 4 Meg x 32 x 4 banks MT46H16M32LG 4 Meg x 32 x 4 banks Options Marking Features V /V DD DDQ V /V = 1.701.95V DD DDQ 1.8V/1.8V H Bidirectional data strobe per byte of data (DQS) Configuration Internal, pipelined double data rate (DDR) 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 architecture two data accesses per clock cycle 16 Meg x 32 (4 Meg x 32 x 4 banks) 16M32 Addressing Differential clock inputs (CK and CK ) JEDEC-standard addressing LF Commands entered on each positive CK edge Plasticgree package DQS edge-aligned with data for READs center- 1 60-ball VFBGA (8mm x 9mm) BF aligned with data for WRITEs 2 90-ball VFBGA (8mm x 13mm) B5 4 internal banks for concurrent operation 2 90-ball VFBGA (8mm x 13mm) BQ Data masks (DM) for masking write data one mask Timing cycle time per byte 5ns CL = 3 (200 MHz) -5 Programmable burst lengths (BL): 2, 4, 8, or 16 6ns CL = 3 (166 MHz) -6 Power Concurrent auto precharge option is supported Standard I /I None DD2 DD6 Auto refresh and self refresh modes Low-power I /I L DD2 DD6 1.8V LVCMOS-compatible inputs Product certification Temperature-compensated self refresh (TCSR) Automotive A Partial-array self refresh (PASR) Operating temperature range Deep power-down (DPD) Industrial (40C to +85C) IT Automotive (40C to +105C) AT Status read register (SRR) Design revision :C Selectable output drive strength (DS) 1. Only available for x16 configuration. Clock stop capability Notes: 2. Only available for x32 configuration. 64ms refresh, 32ms for automotive temperature Table 1: Key Timing Parameters (CL = 3) Speed Grade Clock Rate Access Time -5 200 MHz 5.0ns -6 166 MHz 5.0ns PDF: 09005aef846e285e Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 t67m embedded lpddr 512mb.pdf - Rev. D 2/14 EN 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.512Mb: x16, x32 Automotive LPDDR SDRAM Features Table 2: Configuration Addressing Architecture 32 Meg x 16 16 Meg x 32 Configuration 8 Meg x 16 x 4 banks 4 Meg x 32 x 4 banks Refresh count 8K 8K Row addressing 8K A 12:0 8K A 12:0 Column addressing 1K A 9:0 512 A 8:0 Figure 1: 512Mb Mobile LPDDR Part Numbering MT 46 H 32M16 LF BF -6 A AIT :C Micron Technology Design Revision :C = Third generation Product Family 46 = Mobile LPDDR Operating Temperature IT = Industrial AT = Automotive Operating Voltage H = 1.8/1.8V Product Certification A = Automotive Configuration 32 Meg x 16 Power 16 Meg x 32 Blank = Standard I /I DD2 DD6 L = Low-power I /I DD2 DD6 Addressing LF = JEDEC-standard Cycle Time (CL = 3) t -5 = 5ns CK t -6 = 6ns CK Package Codes BF = 60-ball (8mm x 9mm) VFBGA, green B5 = 90-ball (8mm x 13mm) VFBGA, green BQ = 90-ball (8mm x 13mm) VFBGA, green FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef846e285e Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 t67m embedded lpddr 512mb.pdf - Rev. D 2/14 EN 2012 Micron Technology, Inc. All rights reserved.