MT46H128M16LFDD-48 AIT:C TR

2Gb: x16, x32 Automotive LPDDR SDRAM Features Automotive LPDDR SDRAM MT46H128M16LF 32 Meg x 16 x 4 Banks MT46H64M32LF 16 Meg x 32 x 4 Banks Options Mark Features V /V DD DDQ V /V = 1.701.95V DD DDQ 1.8V/1.8V H Bidirectional data strobe per byte of data (DQS) Configuration Internal, pipelined double data rate (DDR) 128 Meg x 16 (32 Meg x 16 x 4 banks) 128M16 architecture two data accesses per clock cycle 64 Meg x 32 (16 Meg x 32 x 4 banks) 64M32 Addressing Differential clock inputs (CK and CK ) JEDEC-standard LF Commands entered on each positive CK edge Plasticgree package DQS edge-aligned with data for READs center- 60-ball VFBGA (8mm x 9mm) DD aligned with data for WRITEs 90-ball VFBGA (8mm x 13mm) BQ 4 internal banks for concurrent operation Timing cycle time Data masks (DM) for masking write data one mask 4.8ns CL = 3 (208 MHz) -48 per byte Special Options Programmable burst lengths (BL): 2, 4, 8, or 16 Automotive (package-level burn-in) A Operating temperature range Concurrent auto precharge option is supported From 40C to +85C IT Auto refresh and self refresh modes 1 From 40C to +105C AT 1.8V LVCMOS-compatible inputs Design revision :C 2 Temperature-compensated self refresh (TCSR) Partial-array self refresh (PASR) 1. Contact factory for availability. Notes: Deep power-down (DPD) 2. Self refresh supported up to 85 C. Status read register (SRR) Selectable output drive strength (DS) Clock stop capability 64ms refresh 32ms for the automotive temperature range Table 1: Key Timing Parameters (CL = 3) Speed Grade Clock Rate Access Time -48 208 MHz 4.8ns Table 2: Configuration Addressing 2Gb Architecture 128 Meg x 16 64 Meg x 32 Configuration 32 Meg x 16 x 4 banks 16 Meg x 32 x 4 banks Refresh count 8K 8K Row addressing 16K A 13:0 16K A 13:0 Column addressing 2K A11, A 9:0 1K A 9:0 09005aef8541eee0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 t89m auto lpddr.pdf - Rev. I 05/18 EN 2013 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.2Gb: x16, x32 Automotive LPDDR SDRAM Features See Package Block Diagrams for descriptions of signal connections and die configurations for each respective ar- chitecture. Figure 1: 2Gb Mobile LPDDR Part Numbering MT 46 H 64M32 LF KQ -6 A IT :C Micron Technology Design Revision :C = Design generation Product Family 46 = Mobile LPDDR Operating Temperature IT = Industrial (40C to +85C) Operating Voltage AT = Automotive (40C to +105C) H = 1.8/1.8V WT = Wireless (25C to +85C) HC = 1.8/1.2V Special Options (Multiple processing codes are separated Configuration (depth, width) by a space and are listed in hierarchical order.) 128 Meg x 16 Blank = None 64 Meg x 32 A = Automotive 128 Meg x 32 256 Meg x 32 Speed Grade t -48 = 4.8ns CK Addressing t -5 = 5ns CK LF = JEDEC-standard addressing L2 = 2-die stack standard addressing Package Codes L4 = 4-die stack standard addressing DD = 60-ball (8mm x 9mm) VFBGA, green BQ = 90-ball (8mm x 13mm) VFBGA, green KQ = 168-ball (12mm x 12mm) WFBGA, green LE = 168-ball (12mm x 12mm) TFBGA, green FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. 09005aef8541eee0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 t89m auto lpddr.pdf - Rev. I 05/18 EN 2013 Micron Technology, Inc. All rights reserved.