Le79128 Next Generation VoiceEdge Control Processor Next Generation Carrier Chipset (NGCC) APPLICATIONS DESCRIPTION TM Cost effective voice solution for long or short loops The Le79128 Next Generation VoiceEdge Control Processor providing POTS and integrated test capabilities (VCP) is a second generation platform that delivers enhanced call control, self-test and line test capabilities. This latest Applications include: IVD, DLC, CO, Voice-enabled processor works with Microsemi NGCC devices using its SPI DSLAM, PBX/KTS, MDU, MSAP, MSAN interfaces, PCM ports, and GPIO. The Le79128 device provides the same integrated line-testing and feature-set as the Le79112 device, plus additional capabilities such as 4 FEATURES channels of simultaneous line testing and 128 channels of Aggregated call control lowers demand on host micro- improved POTS control. processor This product enables the design of a low-cost, high- 128 channels of call control performance, fully software programmable line interface with Provides expanded line and circuit testing in worldwide applicability. All AC, DC, and signaling parameters conjunction with Microsemis NGCC chipset are programmable. Provides 4 channels of simultaneous line testing The Le79128 device is provided with extensive software and Software interface using VoicePath API-II support, through the LineCare software suite, enabling the designer to develop a fully programmable solution in the least Software downloadable, field upgradeable, expandable amount of time. Serial and parallel host controller interface options RELATED LITERATURE Complete control of up to 16 Octal NGSLAC devices 139366 Le79128-SW NGVCP Software Data Sheet Two master SPI ports 081555 Le79271 NGSLIC Data Sheet 32 General Purpose I/Os 16 configured as chip selects 138884 Le79272 Dual NGSLIC Data Sheet 16 configured for interrupts 081193 Le79238 Octal NGSLAC Data Sheet Two slave PCM highway ports 136868 ZL79258 Octal Ext Ringing NGSLAC Data Sheet Internal PLL and hardware network timing recovery for 126583 NGCC Hardware Design Guide creating analog sampling clocks TM VoicePath API II Reference Guide 3.3 V compliant I/O BLOCK DIAGRAM PCM Highways PLL PCM Slave PCM B Bus 2 ORDERING INFORMATION 4 Clock RST Generator Slave Device Package Packing PCM PCM A/ Bus 1 Redundant 1 6 Le79128KVC Tray 128-pin TQFP (Green) Interrupt To INT Controller Host 1 Le79128KVCT Tape & Reel To 128-pin TQFP (Green) SPI1 SPI1 SLAC DSP Core 2 devices 3 ZL79128GDG2 Tray and HBI 144-pin LBGA Memory SPI/GPI 21 Host Bus Interface CONF SPI2 1. The green package meets RoHS Directive 2002/95/EC of the SPI2 3 4 European Council to minimize the environmental impact of For electrical equipment. Debug and Microsemi GPIO Development Ports use only 32 2. The LBGA package is RoHS-6 compliant. GPIO AUXOUT Linear 1.8V Regulator Document ID : 139365 Date: Nov 7, 2011 Version 2 Protected Document Zarlink Semiconductor, Inc. was acquired by Microsemi Corporation in October 2011 and became a part of its Communications and Medical Products Group (CMPG). Microsemi documents markedPreliminar relate Microsemi to products which are not yet released to production and are identified with anEN suffix in their part number. Such products and their associated Preliminary Data Sheets are supplied only for testing and on the express understanding that (i) such products have not been fully tested or characterized under intended modes of operation and may contain defects (ii) Microsemi makes no representation or warranty regarding such products or technical specifications and (iii) Microsemi disclaims any liability for claims,demands and damage, including and without limitation special, indirect and consequential damages resulting from any loss arising out of the application, use or performance of such products or specifications. Such products and Prelim- inary Data Sheets may be changed or discontinued by Microsemi at any time without notice. US and International Patents Pending.Le79128 Preliminary Data Sheet TABLE OF CONTENTS Applications .1 Features 1 Ordering Information .1 Description 1 Related Literature 1 Block Diagram 1 Table of Contents 2 Connection Diagrams .3 Pin Descriptions .6 Electrical Characteristics .11 Absolute Maximum Ratings 11 Operating Ranges .11 DC Specifications .12 Host Bus Interface (HBI) Overview .13 Transport Layer .14 Interface Addressing .14 Command Structure 15 VCP Direct Page Hardware Register Summary 17 Direct Page (Hardware) Registers .18 Code Loading 26 Host Boot Procedure .26 Application Layer .27 Software (Application Derived) Registers .27 Physical Layer 28 General Purpose Parallel Interface (GPI) .28 Serial Peripheral Interface (SPI) 36 SPI1 and SPI2 Timing 42 PCM Interface .43 The VCP Device Interrupt Report and Service Mechanism 45 Debug Interface .46 Timing Diagram Test Points .46 Troubleshooting at Initial Start-up 47 Physical Dimensions .48 128-Pin TQFP .48 144-Pin LBGA .49 Revision History 50 Version 1 to Version 2 .50 2 Microsemi Corporation - CMPG