ZL40264LDG1

Data Sheet ZL40264 Four output ultra-low additive phase noise PCIe Gen 1 to 5, and UPI/QPI fanout buffer Ordering Information Features ZL40264LDG1 20 pin QFN Trays One differential input which accepts any ZL40264LDF1 20 pin QFN Tape and Reel differential format. Package size: 4 x 4 mm Four differential HCSL outputs -40 C to +85 C Ultra-low additive jitter: 32fs (in 12kHz to 20MHz integration band at 400MHz clock frequency) Applications Supports clock frequencies from 0 to 400MHz PCI Express generation 1/2/3/4/5 clock distribution Supports 2.5V or 3.3V power supplies for HCSL UPI/QPI clock distribution outputs Low jitter clock trees Embedded Low Drop Out (LDO) Voltage regulator Logic translation provides superior Power Supply Noise Rejection Clock and data signal restoration Maximum output to output skew of 50ps High performance microprocessor clock distribution Individual Output Enable pin for each differential Test Equipment pair. Transfers Spread-Spectrum without attenuation OE 3:0 b OUT0 p OUT0 n OUT1 p OUT1 n IN p IN n OUT2 p OUT2 n ZL40264 OUT3 p OUT3 n Figure 1. Functional Block Diagram ZL40264 June 2019 1 2019 Microsemi Corporation Data Sheet ZL40264 Table of Contents Features ..................................................................................................................................... 1 Applications................................................................................................................................ 1 Table of Contents ...................................................................................................................... 2 Pin Diagram ............................................................................................................................... 5 Pin Descriptions ......................................................................................................................... 6 Functional Description ............................................................................................................... 7 Clock Inputs ............................................................................................................................... 7 Clock Outputs .......................................................................................................................... 10 Termination of unused outputs ................................................................................................ 11 Power Consumption ................................................................................................................ 11 Power Supply Filtering ............................................................................................................. 11 Power Supplies and Power-up Sequence ............................................................................... 12 Device Control ......................................................................................................................... 12 Typical phase noise performance ............................................................................................ 13 AC and DC Electrical Characteristics ...................................................................................... 14 Absolute Maximum Ratings ..................................................................................................... 14 Recommended Operating Conditions ..................................................................................... 14 Package Outline ...................................................................................................................... 24 Change history: ........................................................................................................................ 25 ZL40264 June 2019 2 2019 Microsemi Corporation