SY58607UMG-TR

SY58607U 3.2 Gbps Precision, 1:2 LVPECL Fanout Buffer with Internal Termination and Fail Safe Input Features General Description Precision 1:2, 800 mV LVPECL Fanout Buffer The SY58607U is a 2.5V/3.3V, high-speed, fully differential 1:2 LVPECL fanout buffer optimized to Guaranteed AC Performance over Temperature provide two identical output copies with less than 20 ps and Voltage: of skew. The SY58607U can process clock signals as - DC-to >3.2 Gbps Throughput fast as 2.5 GHz or data patterns up to 3.2 Gbps. - <350 ps Propagation Delay (IN-to-Q) The differential input includes Microchips unique, - <20 ps Within-Device Skew 3-lead input termination architecture that interfaces to -<11 0 ps Rise/Fall Times LVPECL, LVDS, or CML differential signals, (AC- or Fail Safe Input DC-coupled) as small as 100 mV (200 mV ) without PP - Prevents Outputs From Oscillating When any level-shifting or termination resistor networks in the Input is Invalid signal path. For AC-coupled input interface applications, an integrated voltage reference Ultra-Low Jitter Design (VREF-AC) is provided to bias the VT pin. The outputs -4 1 fs Additive Phase Jitter are 800 mV LVPECL, with extremely fast rise/fall times High-Speed LVPECL Outputs guaranteed to be less than 110 ps. 2.5V 5% or 3.3V 10% Power Supply Operation The SY58607U operates from a 2.5V 5% supply or Industrial Temperature Range: 40C to +85C 3.3V 10% supply and is guaranteed over the full Available in 16-lead (3 mm x 3 mm) QFN industrial temperature range (40C to +85C). For Package applications that require CML or LVDS outputs, consider Microchips SY58606U and SY58608U, 1:2 Applications fanout buffers with 400 mV and 325 mV output swings respectively. The SY58607U is part of Microchips All SONET Clock and Data Distribution high-speed, Precision Edge product line. Fibre Channel Clock and Data Distribution Gigabit Ethernet Clock And Data Distribution Backplane Distribution Package Type Markets SY58607U Storage 3 mm x 3 mm QFN-16 (M) ATE (Top View) Test and Measurement Enterprise Networking Equipment High-End Servers Access 16 15 14 13 Metro Area Network Equipment IN 1 12 Q0 VT 2 11 /Q0 Q1 VREF-AC 3 10 /IN 4 9 /Q1 5 6 7 8 United States Patent No. RE44,134 2019 Microchip Technology Inc. 1DS20006227A-page VCC VCC GND GND GND GND VCC VCCSY58607U Functional Block Diagram IN Q V T /Q /IN VREF-AC DS20006227A-page 2 2019 Microchip Technology Inc.