SY100S834/SY100S834L ( 1, 2, 4) or (2, 4, 8) Clock Generation Chip Precision Edge General Description The SY100S834/L is low skew (1, 2, 4) or (2, 4, 8) Precision Edge clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are Features synchronous to each other, therefore, the common output 3.3V (SY100S834L) and 5V (SY100S834) power edges are all precisely aligned. The devices can be driven supply options by either a differential or single-ended ECL or, if positive 50ps output-to-output skew power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC- Synchronous enable/disable coupled into the device. If a single-ended input is to be Master reset for synchronization used, the VBB output should be connected to the CLK Internal 75K input pulldown resistors input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference Available in 16-pin SOIC package for the input of the SY100S834/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. Truth Table The Function Select (FSEL) input is used to determine CLK MR Function EN what clock generation chip function is. When FSEL input is Z L L Divide LOW, SY100S834/L functions as a divide by 2, by 4 and by 8 clock generation chip. However, if FSEL input is ZZ H L Hold Q 02 HIGH, it functions as a divide by 1, by 2 and by 4 clock X X H Reset Q 02 generation chip. This latter feature will increase the clock frequency by two folds. Notes: Z = LOW-to-HIGH transition. The common enable (EN) is synchronous so that the ZZ = HIGH-to-LOW transition. internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal F Q Outputs Q Outputs Q Outputs SEL 0 1 2 clock when the device is enabled/disabled as can happen L Divide by 2 Divide by 4 Divide by 8 with an asynchronous control. An internal runt pulse could H Divide by 1 Divide by 2 Divide by 4 lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S834/Ls in a system. Data sheets and support documentation can be found on Micrels web site at www.micrel.com. Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY100S834/SY100S834L Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish SY100S834ZC Z16-2 Commercial SY100S834ZC Sn-Pb (1) SY100S834ZCTR Z16-2 Commercial SY100S834ZC Sn-Pb SY100S834LZC Z16-2 Commercial SY100S834LZC Sn-Pb (1) SY100S834LZCTR Z16-2 Commercial SY100S834LZC Sn-Pb SY100834ZI Z16-2 Industrial SY100S834ZI Sn-Pb (1) SY100834ZITR Z16-2 Industrial SY100S834ZI Sn-Pb SY100834LZI Z16-2 Industrial SY100S834LZI Sn-Pb (1) SY100834LZITR Z16-2 Industrial SY100S834LZI Sn-Pb SY100S834ZG with NiPdAu (2) SY100834ZG Z16-2 Industrial Pb-Free bar-line indicator Pb-Free SY100S834ZG with NiPdAu (1, 2) SY100834ZGTR Z16-2 Industrial Pb-Free bar-line indicator Pb-Free (2) SY100S834LZG with NiPdAu SY100834LZG Z16-2 Industrial Pb-Free bar-line indicator Pb-Free (1, 2) SY100S834LZG with NiPdAu SY100834LZGTR Z16-2 Industrial Pb-Free bar-line indicator Pb-Free Notes: 1. Tape and reel. 2. Pb-Free package is recommended for new designs. Pin Configuration 16-Pin SOIC (Z16-2) M9999-060911 June 2011 2 hbwhelp micrel.com or (408) 955-1690