Product Information

PL133-97QC

PL133-97QC electronic component of Microchip

Datasheet
Clock Buffer 9-Output CMOS Buffer in QFN Package

Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1040: USD 0.702 ea
Line Total: USD 730.08

0 - Global Stock
MOQ: 1040  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 800
Multiples : 1

Stock Image

PL133-97QC
Microchip

800 : USD 1.0435
1000 : USD 1.0372
2000 : USD 1.0309
2500 : USD 1.0245
3000 : USD 1.018
4000 : USD 1.0115
5000 : USD 1.0049
10000 : USD 0.9982
20000 : USD 0.9916
50000 : USD 0.9849

0 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1

Stock Image

PL133-97QC
Microchip

1 : USD 1.1292
25 : USD 0.9123
80 : USD 0.8348

     
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RoHS - XON
Icon ROHS
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Cnhts
Hts Code
Mxhts
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PL133-97 Low-Power DC to 150MHz 1:9 Fanout Buffer IC FEATURES DESCRIPTION The PL133-97 is an advanced fanout buffer design for 1:9 LVCMOS output fanout buffer for DC to 150MHz high performance, low-power, small form factor applica- 8mA Output Drive Strength tions. The PL133-97 accepts a reference clock input from Low power consumption for portable applications DC to 150MHz and provides 6 outputs of the same fre- Low input-output delay quency. Output-Output skew less than 250ps The PL133-97 is offered in a QFN-16L 3x3mm package Low Additive Phase Jitter of 60fs RMS and it offers the best phase noise, additive jitter perfor- 2.5V to 3.3V, 10% operation mance, and lowest power consumption of any comparable 1.8V 10% operation up to 67MHz IC. Operating temperature range from -40C to 85C Available in 16-Pin QFN GREEN/RoHS package The PL133-97 outputs can be disabled to a high imped- ance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled. CLK8 is a free running output that remains enabled when the OE pin is pulled low. BLOCK DIAGRAM AND PACKAGE PINOUT CLK8 CLK1 CLK2 12 11 10 9 CLK7 13 8 CLK4 CLK3 14 7 CLK8 GND REF CLK4 15 6 REF OE CLK5 CLK9 16 5 CLK3 1 2 3 4 CLK6 CLK7 CLK9 QFN-16L OE Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 05/22/14 Page 1 CLK1 CLK6 VDD VDD GND GND CLK2 CLK5 PL133-97 Low-Power DC to 150MHz 1:9 Fanout Buffer IC PIN DESCRIPTIONS Name QFN-16L Type Description REF 15 I Input reference frequency. CLK1 1 O Buffered clock output CLK2 4 O Buffered clock output CLK3 5 O Buffered clock output CLK4 8 O Buffered clock output CLK5 9 O Buffered clock output CLK6 12 O Buffered clock output CLK7 13 O Buffered clock output CLK8 14 O Buffered clock output, free running, does not disable with OE. CLK9 16 O Buffered clock output VDD 2, 11 P VDD connection GND 3, 7, 10 P GND connection OE 6 I Output Enable Control Input with 130K Pull-Up ePad - - Center Pad for Thermal Relief. Connect to GND. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 05/22/14 Page 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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