MT89L80AP1

TM CMOS ST-BUS Family MT89L80 Digital Switch Data Sheet Sept. 2006 Features 3.3 volt supply Ordering Information 5 V tolerant inputs and TTL compatible outputs. MT89L80ANR 48 Pin SSOP Tape & Reel MT89L80APR 44 Pin PLCC Tape & Reel 256 x 256 channel non-blocking switch MT89L80AP 44 Pin PLCC Tubes MT89L80AN 48 Pin SSOP Tubes Accepts serial streams at 2.048 Mb/s MT89L80APR1 44 Pin PLCC* Tape & Reel Per-channel three-state control MT89L80ANR1 48 Pin SSOP* Tubes MT89L80AN1 48 Pin SSOP* Tubes Patented per channel message mode MT89L80AP1 44 Pin PLCC* Tubes *Pb Free Matte Tin Non-multiplexed microprocessor interface -40 C to +85 C Zarlink ST-BUS compatible Low power consumption: typical 15 mW Description Pin compatible with the MT8980DP This VLSI CMOS device is designed for switching PCM-encoded voice or data, under microprocessor Applications control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to Key telephone systems 256 64 kbit/s channels. Each of the eight serial inputs PBX systems and outputs consist of 32 64kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream. In Small and medium voice switching systems addition, the MT89L80 provides microprocessor read and write access to individual ST-BUS channels. ** V V ODE RESET DD SS C4i F0i Frame Output Counter STo0 STi0 MUX STo1 STi1 Parallel Serial STo2 Data STi2 to to STo3 Memory STi3 Serial Parallel STo4 STi4 Control Register Converter Converter STo5 Connection STi5 Memory STo6 STi6 STo7 STi7 Control Interface DS CS R/W A5/ DTA D7/ CSTo A0 D0 ** for 48-pin SSOP only Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.MT89L80 Data Sheet 1 48 CSTo V SS 2 47 ODE DTA 3 46 STi0 STo0 STi1 4 45 STo1 STi2 5 STo2 44 STi3 7 39 STo3 NC 6 43 NC STi4 8 38 STo4 STi3 7 42 STo3 STi5 9 37 STo5 8 STo4 STi6 10 STi4 41 36 STo6 STi7 11 STi5 9 40 35 STo7 STo5 V 12 V 10 39 34 STi6 STo6 DD SS F0i 13 33 D0 STi7 11 38 STo7 C4i 14 32 D1 V 12 37 V DD SS A0 15 31 D2 13 36 V RESET DD A1 16 D3 30 14 35 D0 F0i 17 A2 29 D4 15 34 D1 C4i 16 33 A0 D2 A1 17 32 D3 18 31 D4 A2 NC 19 30 NC A3 20 29 D5 A4 21 28 D6 44 PIN PLCC 22 D7 A5 27 23 26 CS DS R/W 24 25 V SS 48 PIN SSOP (JEDEC MO-118, 300mil Wide) Figure 2 - Pin Connections Pin Description Pin Name Description 44 48 PLCC SSOP 22 DTA Data Acknowledgment (5 V Tolerant Three-state Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. 3-5 3-5 STi0-2 ST-BUS Inputs 0 to 2 (5 V-tolerant Inputs). Serial data input streams. These streams have data rates of 2.048 Mbit/s with 32 channels. 7-11 7-11 STi3-7 ST-BUS Inputs 3 to 7 (5 V-tolerant Inputs). Serial data input streams. These streams may have data rates of 2.048 Mbit/s with 32channels. 12 12,36 V +3.3 Volt Power Supply. DD 13 RESET Device Reset (5 V-tolerant input). This pin is only available for the 48-pin SSOP package.This active low input puts the device in its reset state. It clears the internal counters and registers. All ST-BUS outputs are set to the high impedance state. In normal operation. The RESET pin must be held low for a minimum of 100nsec to reset the device. Internal pull-up. 13 14 F0i Frame Pulse (5 V-tolerant Input). This is the input for the frame synchronization pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i. 2 Zarlink Semiconductor Inc. NC 18 6 NC A3 19 STi2 5 A4 20 STi1 4 A5 21 3 STi0 DS 22 2 DTA R/W 23 1 CSTo 24 CS 44 ODE 25 D7 43 STo0 D6 26 42 STo1 D5 41 27 STo2 NC 28 40 NC