MT88L70ASR1

MT88L70 3 Volt Integrated DTMF Receiver Data Sheet August 2005 Features 2.7 - 3.6 volt operation Ordering Information Complete DTMF receiver MT88L70AE 18 Pin PDIP Tubes MT88L70AS 18 Pin SOIC Tubes Low power consumption MT88L70AN 20 Pin SSOP Tubes MT88L70ASR 18 Pin SOIC Tape & Reel Internal gain setting amplifier MT88L70ANR 20 Pin SSOP Tape & Reel Adjustable guard time MT88L70AE1 18 Pin PDIP* Tubes MT88L70AN1 20 Pin SSOP* Tubes Central office quality MT88L70ANR1 20 Pin SSOP* Tape & Reel MT88L70AS1 18 Pin SOIC* Tubes Power-down mode MT88L70ASR1 18 Pin SOIC* Tape & Reel Inhibit mode * Pb Free Matte Tin Functionally compatible with Zarlinks MT8870D -40C to +85C Description Applications The MT88L70 is a complete 3 Volt, DTMF receiver Paging systems integrating both the bandsplit filter and digital decoder Repeater systems/mobile radio functions. The filter section uses switched capacitor techniques for high and low group filters the decoder Credit card systems uses digital counting techniques to detect and decode Remote control all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on chip provision of Personal computers a differential input amplifier, clock oscillator and latched Telephone answering machine three-state bus interface. VDD VSS VRef INH Bias PWDN Circuit VRef Buffer Q1 Chip Chip High Group Digital Code Power Bias Filter Detection Converter Q2 Algorithm and Latch IN + Dial Zero Crossing Tone Detectors Q3 Filter IN - Low Group GS Q4 Filter to all St Steering Chip GT Logic Clocks OSC1 OSC2 St/GT ESt STD TOE Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.MT88L70 Data Sheet 1 18 20 IN+ VDD IN+ 1 VDD 2 17 2 19 IN- St/GT IN- St/GT 16 18 GS 3 ESt GS 3 ESt 15 17 VRef 4 StD VRef 4 StD 5 14 5 16 INH Q4 INH NC PWDN 13 15 6 Q3 PWDN 6 Q4 12 14 7 Q2 NC 7 OSC1 Q3 11 13 OSC2 8 Q1 OSC1 8 Q2 10 12 VSS 9 TOE OSC2 9 Q1 11 VSS 10 TOE 18 PIN PDIP/SOIC 20 PIN SSOP Figure 2 - Pin Connections Pin Description Pin Name Description 18 20 11 IN+ Non-Inverting Op-Amp (Input). 22 IN- Inverting Op-Amp (Input). 33 GS Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. 44 V Reference Voltage (Output). Nominally V /2 is used to bias inputs at mid-rail (see Figure 5 Ref DD and Figure 6). 55 INH Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. 6 6 PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down. 78 OSC1 Clock (Input). 89 OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit. 910 V Ground (Input). 0 V typical. SS 10 11 TOE Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled up internally. 11- 12- Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the 14 15 last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance. 15 17 StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated returns to logic low when the voltage on St/GT falls below V TSt. 16 18 ESt Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 2 Zarlink Semiconductor Inc.