MT8870DSR1

MT8870D/MT8870D-1 2 ISO -CMOS Integrated DTMF Receiver Data Sheet October 2006 Features Complete DTMF Receiver Ordering Information Low power consumption MT8870DE 18 Pin PDIP Tubes MT8870DS 18 Pin SOIC Tubes Internal gain setting amplifier MT8870DN 20 Pin SSOP Tubes MT8870DSR 18 Pin SOIC Tape & Reel Adjustable guard time MT8870DNR 20 Pin SSOP Tape & Reel Central office quality MT8870DN1 20 Pin SSOP* Tubes MT8870DE1 18 Pin PDIP* Tubes Power-down mode MT8870DS1 18 Pin SOIC* Tubes MT8870DNR1 20 Pin SSOP* Tape & Reel Inhibit mode MT8870DSR1 18 Pin SOIC* Tape & Reel MT8870DE1-1 18 Pin PDIP* Tubes Backward compatible with MT8870C/MT8870C-1 MT8870DS1-1 18 Pin SOIC* Tubes MT8870DSR1-1 18 Pin SOIC* Tape & Reel *Pb Free Matte Tin Applications -40C to +85C Receiver system for British Telecom (BT) or CEPT Spec (MT8870D-1) Description Paging systems The MT8870D/MT8870D-1 is a complete DTMF Repeater systems/mobile radio receiver integrating both the bandsplit filter and digital Credit card systems decoder functions. The filter section uses switched capacitor techniques for high and low group filters Remote control the decoder uses digital counting techniques to detect Personal computers and decode all 16 DTMF tone-pairs into a 4-bit code. Telephone answering machine VDD VSS VRef INH Bias PWDN Circuit VRef Buffer Q1 Chip Chip High Group Digital Power Bias Code Filter Detection Converter Q2 Algorithm and Latch IN + Dial Zero Crossing Tone Detectors Q3 Filter IN - Low Group GS Q4 Filter to all St Steering Chip GT Logic Clocks OSC1 OSC2 St/GT ESt STD TOE Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2006, Zarlink Semiconductor Inc. All Rights Reserved.MT8870D/MT8870D-1 Data Sheet External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface. 18 20 IN+ 1 VDD IN+ 1 VDD 2 17 2 19 IN- St/GT IN- St/GT 16 18 GS 3 ESt GS 3 ESt 15 17 VRef 4 StD VRef 4 StD 5 5 INH 14 Q4 INH 16 NC PWDN 6 13 Q3 PWDN 6 15 Q4 OSC1 7 12 Q2 NC 7 14 Q3 OSC2 8 11 Q1 OSC1 8 13 Q2 VSS 9 10 TOE OSC2 9 12 Q1 VSS 10 11 TOE 20 PIN SSOP 18 PIN PLASTIC DIP/SOIC Figure 2 - Pin Connections Pin Description Pin Name Description 18 20 11 IN+ Non-Inverting Op-Amp (Input). 22 IN- Inverting Op-Amp (Input). 33 GS Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. 44 V Reference Voltage (Output). Nominally V /2 is used to bias inputs at mid-rail (see Fig. 6 Ref DD and Fig. 10). 55 INH Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. 66 PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down. 78 OSC1 Clock (Input). 89 OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit. 910 V Ground (Input). 0 V typical. SS 10 11 TOE Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled up internally. 11- 12- Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the 14 15 last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance. 15 17 StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated returns to logic low when the voltage on St/GT falls below V . TSt 16 18 ESt Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 2 Zarlink Semiconductor Inc.