MEC1404-NU

MEC140x/1x Keyboard and Embedded Controller Products for Notebook PC - Programmable clock frequencies: 48MHz, Common Features 12MHz, 3MHz, and 1MHz 3.3V Operation -Sleep mode ACPI 3.0 Compliant - 2-wire Debug Interface (ICSP) PC2001 compliant - 6 Breakpoints (4-instruction 2-data) VTR (standby) and VBAT Power Planes - Enhanced to Support Debug in Heavy and - Low Standby Current in Sleep Mode Deep Sleep States Connected Standby Support Trace FIFO Debug Port (TFDP) 32kHz Clock Source Internal DMA Controller - Internal 32kHz Oscillator - Hardware or Firmware Flow Control - External 32kHz Clock Source - Firmware Initiated Memory-to-Memory transfers - 32kHz Crystal (XTAL) Supported - 7-Hardware DMA Channels support three - Single-Ended 32kHz Clock Source SMBus Master/Slave Controllers and one SPI Controller LPC Host Interface - Hardware CRC-32 Generator on Channel 0 - LPC Specification 1.1 Compatible Secure Boot ROM Loader - LPC I/O and Memory Cycles Decoded - 4 Code Images in Shared Flash Supported - Supports optional signals: CLKRUN , LPCPD , SERIRQ, SMI , EC SCI (ACPI PME Event) - Crisis Recovery over Keyboard matrix Scan Pins - Supports 19.2 MHz to 33 MHz nominal bus clock - Supports CRC-32 and AES-128 Encryption speeds Vectored Interrupt Controller Configuration Register Set - Maskable Interrupt controller - Compatible with ISA Plug-and-Play Standard - Maskable Hardware Wake-Up Events - EC-Programmable Base Address - Supports legacy aggregated mode 8042 Emulated Keyboard Controller - Supports Vector Generation per Status Bit - 8042 Style Host Interface Programmable 16-bit Counter/Timer Interface - Port 92 Legacy A20M Support - Four 16-bit Auto-reloading Counter/Timer - Fast GATEA20 & Fast CPU RESET Instances System to EC Message Interface - Two Operating Modes per Instance: Timer and One-shot. - One Embedded Memory Interface 32-bit RTOS Timer - Host Serial or Parallel IRQ Source - Runs Off 32kHz Clock Source - Provides Two Windows to On-Chip SRAM for Host Access - Continues Counting in all the Chip Sleep States Regardless of Processor Sleep State - Two Register Mailbox Command Interface - Counter is Halted when Embedded Controller is - Mailbox Registers Interface Halted (e.g., JTAG debugger active, break - Thirty-two 8-Bit Scratch Registers points) - Two Register Mailbox Command Interface - Generates wake-capable interrupt event - Two Register SMI Source Interface Watch Dog Timer (WDT) - Five ACPI Embedded Controller Interfaces Hibernation Timer Interface - Four EC Interfaces - One 32.768 KHz Driven Timer - One Power Management Interface - Programmable Wake-up from 0.5ms to 128 Min- MIPS32 M14K Microcontroller Core utes - microMIPS-Compatible Instruction Set Week Timer - High-performance Multiply/Divide Unit - System Power Present Input Pin 2015 - 2016 Microchip Technology Inc. DS00001956E-page 1MEC140x/1x - Week Alarm Event only generated when Sys- Power-Fail Status Register tem Power is Available Port 80 BIOS Debug Port - Power-up Event - Two Ports, Assignable to Any LPC IO Address - Week Alarm Interrupt with 1 Second to 8.5 Year - 24-bit Timestamp with Adjustable Timebase Time-out - 16-Entry FIFO - Sub-Week Alarm Interrupt with 0.50 Seconds - PECI Interface 3.0 72.67 hours time-out Two Programmable Comparators - 1 Second and Sub-second Interrupts - 8 Bit Resolution Battery-Powered General Purpose Output (BGPO) - Independent Outputs per Comparator VBAT-Powered Control Interface (VCI) - Option to Use Pin or Programmable Voltage Ref- - 2 Active-low VCI Inputs erence Input - 1 Active-high VCI Input - Can be used for Thermistor Voltage Sensing - 1 Active-high VCI Output Pin Integrated Standby Power Reset Generator - Optional filter and latching XNOR Test Mode Product Dependent Features Enhanced Serial Peripheral Interface (eSPI) - Independent Hardware Driven PS/2 Ports - Intel eSPI Specification compliant - Fully functional on Main and/or Suspend Power - Supports four channels/interfaces: - PS/2 Edge Wake Capable - Peripheral channel Interface - 3.6V Tolerant I/O Suitable for Internal Board Routing - Virtual Wire Interface General Purpose I/O Pins - Out of Band Channel Interface - Inputs - Flash Channel Interface - Asynchronous rising and falling edge wakeup - Supports EC Bus Master to Host Memory detection Interrupt High or Low Level Internal Memory -Outputs: - Boot ROM - Push Pull or Open Drain output - 32 kB Data Optimized SRAM - Programmable power well emulation - Code Optimized SRAM Options from 96 kB to - Pull up or pull down resistor control 160 kB - Automatically disabling pull-up resistors when - 64 Bytes Battery Powered SRAM output driven low Keyboard Matrix Scan Controller - Automatically disabling pull-down resistors - Supports 18x8 Matrix when output driven high - Pre-Drive Mode Supported - Group- or individual control of GPIO data. Up To Three EC-based SMBus 2.0 Host Controllers Up To Three LEDs - Allows Master or Dual Slave Operation - Programmable Blink Rates - Controllers are Fully Operational on Standby - Piecewise Linear Breathing LED Output Control- Power ler 2 C Datalink Compatibility Mode -I - Provides for programmable rise and fall - Multi-Master Capable waveforms - Supports Clock Stretching - Operational in EC Sleep States - Programmable Bus Speeds One Serial Peripheral Interface (SPI) Controller - 1 MHz Capable - Master Only SPI Controller - SMBus Time-outs Interface - Mappable to three ports (only 1 port active at a - Up to 6 Port Flexible Multiplexing time) - Up to 5 ports with 1.8V or 3.3V Configurable - 1 shared SPI Interface. Input Threshold - 1 General Purpose SPI Interface (package - 1 port with VTT level signaling (i.e., AMD SB- dependent) TSI Port) - 1 Crisis recovery SPI Interface (located on - Supports DMA Network Layer Keyboard Matrix Scan connector) Up To Two PS/2 Controllers - Dual and Quad I/O Support DS00001956E-page 2 2015 - 2016 Microchip Technology Inc.