MEC1322-LZY-C0

MEC1322 Keyboard and Embedded Controller for Notebook PC 8042 Style Host Interface Product Features - Mailbox Registers Interface ARM Cortex -M4 Processor Core - Forty-three 8-Bit scratch registers - 32-Bit ARM v7-M Instruction Set Architecture - Two Register Mailbox Command Interface - Hardware Floating Point Unit (FPU) - Two Register SMI Source Interface - Single 4GByte Addressing Space (Von Neu- Two ACPI Embedded Controller Interface - 1 or 4 Byte Data transfer capable mann Model) - Little-Endian Byte Ordering ACPI Power Management Interface - Bit-Banding Feature Included - SCI Event-Generating Functions - NVIC Nested Vectored Interrupt Controller Embedded Memory Interface - Up to 240 Individually-Vectored Interrupt Sources - Host Serial IRQ Source Supported - Provides Two Windows to On-Chip SRAM for - 8 Levels of Priority, Individually Assignable By Vector Host Access - Chip-Level Interrupt Aggregator supported, to Two Register Mailbox Command Interface expand number of interrupt sources or reduce Battery Backed (VCC0/VBAT) Resources number of vectors - Power Fail Register - System Tick Timer - Power-Fail Status Register - Complete ARM-Standard Debug Support - Battery backed 64 byte memory - JTAG-Based DAP Port, Comprised of SWJ-DP and Real Time Clock (RTC) AHB-AP Debugger Access Functions - VCC0 (VBAT) Powered - Full DWT Hardware Functionality: 4 Data - 32KHz Crystal Oscillator Watchpoints and Execution Monitoring - Full FPB Hardware Breakpoint Functionality: 6 - 32KHz Clock output available under VCC1 Execution Breakpoints and 2 Literal (Data) power Breakpoints - Time-of-Day and Calendar Registers - Comprehensive ARM-Standard Trace Sup- - Programmable Alarms port - Supports Leap Year and Daylight Savings - Full DWT Hardware Trace Functionality for Time Watchpoint and Performance Monitoring Hibernation Timers - Full ITM Hardware Trace Functionality for General Purpose Analog to Digital Converter Instrumented Firmware Support and Profiling - 10-bit conversion precision - Full ETM Hardware Trace Functionality for - 10-bit conversion per channel is completed in Instruction Trace less than 12us - Full TPIU Functionality for Trace Output - 5 ADC channels Communication - 10-bit Conversion with 2.9mV resolution 128K SRAM (Code or Data) - 0 to 3.3 VDC Conversion Range - 96K Optimized for Code - Optional continuous sampling at a programmable - 32K Optimized for Data rate LPC Interface - Internal Analog Voltage Reference (3.0V +/- - Supports LPC Bus frequencies of 19MHz to 1%) 33MHz Watch Dog Timer - LPC I/O Cycles Decoded Four Programmable 16-bit and Two 32-bit Timers - LPC Memory Cycles Decoded - Wake-capable Auto-reloading Timers - Clock Run Support Four Independent Hardware Driven PS/2 Ports -Serial IRQ - Fully functional on Main and/or Suspend - ACPI SCI interface Power - SMI output - PS/2 Edge Wake Capable Two SPI Memory Interfaces Four Programmable Pulse-Width Modulator Out- - 3-pin Full Duplex serial communication interface puts - Two Private and Two Shared Chip Selects - Independent Clock Rates - DMA Support - 16-Bit Duty Cycle Granularity - Operational in both Full on and Standby modes 2014 - 2015 Microchip Technology Inc. DS00001719D-page 1MEC1322 Four EC-based SMBus 2.0 Host Controllers Description - Allows Master or Dual Slave Operation The MEC1322 incorporates a high-performance 32-bit - Controllers are Fully Operational on Standby Cortex -M4 embedded microcontroller with 128 ARM Power 2 Kilobytes of SRAM and 32 Kilobytes of Boot ROM. It - DMA-driven I C Network Layer Hardware 2 communicates with the system host using the Intel -I C Datalink Compatibility Mode Low Pin Count (LPC) bus. - Multi-Master Capable - Supports Clock Stretching The MEC1322 has two SPI memory interfaces that - Programmable Bus Speeds allow the EC to read its code from external SPI flash - 400 KHz Fast-mode Capable memory: private SPI and/or shared SPI. The Shared - 1 Mbps Fast-mode Plus Capable SPI interface allows for EC code to be stored in a - Hardware Bus AccessFairnes Interface shared SPI chip along with the system BIOS. The pri- - SMBus Time-outs Interface vate SPI memory interface provides for a dedicated -5 Ports SPI flash that is only accessible by the EC. - 2 Port Flexible Multiplexing The MEC1322 provides support for loading EC code PECI 3.0 Interface from the private or shared SPI flash device on a VCC1 Keyboard Matrix Scan Interface power-on. Before executing the EC code loaded from a - 18 x 8 Interrupt/Wake Capable Multiplexed SPI Flash Device, the MEC1322 validates the EC code Keyboard Scan Matrix using a digital signature encoded according to PKCS - Row Predrive Option 1. The signature uses RSA-2048 encryption and Four Breathing/Blinking LED Interfaces SHA-256 hashing. This provides automated detection - Programmable Blink Rates of invalid EC code that may be a result of malicious or - Piecewise Linear Breathing LED Output Con- accidental corruption. It occurs before each boot of the troller host processor, thereby ensuring a HW based root of - Operational in EC Sleep States trust not easily thwarted via physical replacement Dual Fan Tachometer Inputs attack. RPM-Based Fan Speed Control Algorithm - Utilizes one TACH input and one PWM output The MEC1322 is directly powered by two separate sus- - 3% accurate from 500 RPM to 16k RPM pend supply planes (VBAT and VCC1) and senses the - Automatic Tachometer feedback runtime power plane (VCC) to provide Instant On and - Aging Fan or Invalid Drive Detection system power management functions. It also contains - Spin Up Routine an integrated VCC1 Reset Interface and a system - Ramp Rate Control Power Management Interface that supports low-power - RPM-based Fan Speed Control Algorithm states and can drive state changes as a result of hard- Fast GATEA20 & Fast CPU RESET ware wake events. RSMRST Functionality Supporting System Deep Sleep - Compatible with south bridge SUS- CLK/RSMRST gating rules - Replacement 32K distribution available when RSMRST is asserted Integrated Power-on Reset Generator - VCC1 RST open drain output - Accepts External driven Reset Anti-Glitch Protection on Power-on All Blocks Support Low Power Sleep Modes General Purpose Input/Output Pins - Low Power - High Configurability Two pin Debug Port with standard 16C550A regis- ter interface - Accessible from both Host and EC BC-Link Interconnection Bus - One High Speed Bus Master Controller Package Options - 128-pin VTQFP - 132-pin DQFN - 144-pin WFBGA DS00001719D-page 2 2014 - 2015 Microchip Technology Inc.