HV7355DB1 Supertex inc. 150V, 1.5A, Unipolar Ultrasound Pulser Demoboard This demoboard datasheet describes how to use the General Description HV7355DB1 to generate the basic high voltage pulse The HV7355 is a monolithic eight-channel, high-speed, waveform as an ultrasound transmitting pulser. high voltage, unipolar ultrasound transmitter pulser. This integrated, high performance circuit is in a single, The HV7355 circuit uses DC-coupling from a 3.3V logic input 8x8x0.9mm, 56-lead QFN package. to output TX0~7 internally, therefore the chip needs three sets of voltage supply rails: V (+3.3V), V /V (+/-5.0V) The HV7355 can deliver guaranteed 1.5A source and sink LL DD SS and V (up to +150V). The V high voltage supply can be current to a capacitive transducer with 0 to +150V peak PP PP changed rather quickly, compared to the capacitor gate- voltage. It is designed for medical ultrasound imaging and coupled driving pulsers. This direct coupling topology of the ultrasound material NDT applications. It can also be used gate drivers not only saves two high voltage capacitors per as a high voltage driver for other piezoelectric or capacitive channel, but also makes the PCB layout easier. MEMS transducers, or for ATE systems and pulse signal generators as a signal source. The control signal logic-high voltage should be the same as the V voltage of the IC, and the logic-low should be The HV7355s circuitry consists of controller logic circuits, LL referenced to GND. level translators, gate driving buffers and a high current and high voltage MOSFET output stage. The output stages of The HV7355DB1 output waveforms can be displayed using each channel are designed to provide peak output currents an oscilloscope by connecting the scope probe to the test typically over 1.5A for pulsing, with up to 150V swings. The points TX0~7 and GND. The soldering jumper can select upper limit frequency of the pulser waveform is dependent whether or not to connect the on-board dummy load, a upon the load capacitance. With different capacitance load 330pF capacitor paralleling with a 2.5k resistor. The test conditions the maximum output frequency is about 20MHz. points can be used to connect the users transducer to easily evaluate the pulser. Block Diagram +3.3V +5.0V +5.0 to 150V +3.3V VLL AVDD VDD CPF VPP LR VPF EN PWR VSS EXCLK VDD VPP MC CWD LT CLK OSC IN IN0 VPF TX0 40MHz VDD Q0 VDD Waveform EN R2 Generator LT Dummy Load CPLD RGND C4 R3 330pF 2.5k VDD VPP VPP 6 GND JTAG LT IN7 VPF TX7 TX7 VDD VDD Q7 CW Q 7:0 SET LR LT WAVE Data LE RTZ RGND Latch FREQ PWR CS SEL RGND Shift EN SCK EN Register SUB CW/RTZ Q7 D0 SDO SDI VSUB GND VSS -5.0V Doc. DSDB-HV7355DB1 Supertex inc. B070314 www.supertex.comHV7355DB1 This feedback may cause oscillations or spurious waveform The PCB Layout Techniques shapes on the edges of signal transitions. Since the input The large thermal pad at the bottom of the HV7355 package operates with signals down to 3.3V, even small coupling is internally connected to the ICs substrate (VSUB). This voltages may cause problems. Use of a solid ground plane thermal pad should be connected to 0V or GND externally and good power and signal layout practices will prevent this on the PCB. The designer needs to pay attention to the con- problem. Also ensure that the circulating ground return cur- necting traces on the outputs TX0~7, as the high-voltage rent from a capacitive load cannot react with common induc- and high-speed traces. In particular, controlled-impedance tance to create noise voltages in the input logic circuitry. to the ground plane and more trace spacing needs to be ap- plied in this situation. Testing the Integrated Pulser The HV7355 pulser demoboard should be powered up with High-speed PCB trace design practices that are compatible a DC power supplie that has current limiting functions. with about 50 to 100MHz operating speeds are used for the demo board PCB layout. The internal circuitry of the HV7355 To meet the typical loading conditions, the on-board dummy can operate at quite a high frequency, with the primary speed load 330pF//2.5k should be connected to the high voltage limitation being load capacitance. Because of this high pulser output through the solder jumper when using an oscil- speed and the high transient currents that result when driv- loscopes high impedance probe. To evaluate different load- ing capacitive loads, the supply voltage bypass capacitors ing conditions, the values of the RC within the current and and the driver to the FETs gate-coupling capacitors should power limit of the device may be changed. be as close to the pins as possible. The GND pin should have low inductance feed-through via connections that are In order to drive the users piezo transducers with a cable, connected directly to a solid ground plane. The VDD, VSS, one should match the output load impendence properly to VPP and CPP voltage-supply and/or bypass capacitor pins avoid cable and transducer reflections. A 70 to 75 coaxial can draw fast transient currents of up to 2.0A, so they should cable is recommended. The coaxial cable end should be sol- be provided with a low-impedance bypass capacitor at the dered to TX0~7 and GND directly with very short leads. If a chip s pins. A ceramic capacitor of 1.0 to 2.0F may be used. users load is being used, the on-board dummy load should Only VPP to GND capacitors need be high voltage. CPF to be disconnected by cutting the small shorting copper trace in VPP capacitors only need be low voltage. Minimize the trace between the zero resistors (R2, R12 etc.) pads. They are length to the ground plane, and insert a ferrite bead in the shorted by factory default. power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive All of the on-board test points are designed to work with the to jitter and noise when using multiple HV7355 ICs, insert high impedance probe of the oscilloscope. Some probes another ferrite bead between each chips supply line. may have limited input voltage. When using the probe on these high voltage test-points, make sure that V voltages Pay particular attention to minimizing trace lengths and PP do not exceed the probe limit. Using the high impendence using sufficient trace width to reduce inductance. Surface oscilloscope probe for the on-board test points, it is impor- mount components are highly recommended. Since the out- tant to have short ground leads to the circuit board ground put impedance of the HV7355s high voltage power stages plane. is very low, to obtain better waveform integrity at the load terminals after long cables, in some cases it may be desir- able to add a small value resistor in series with the outputs TX0~7. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load. Be aware of the parasitic coupling from the outputs to the input signal termi- nals of the HV7355. Doc. DSDB-HV7355DB1 Supertex inc. B070314 2 www.supertex.com