Core429-SA

ARINC 429 Bus Interface Core Deliverables Product Summary Evaluation Version Compiled RTL Simulation Model, Compliant Intended Use with the Actel Libero Integrated Design ARINC 429 Transmitter (Tx) Environment (IDE) ARINC 429 Receiver (Rx) Netlist Version Structural VHDL and Verilog Netlists Key Features RTL version Supports ARINC Specification 429-16 VHDL or Verilog Core Source Code Synthesis Scripts Configurable up to 16 Rx and 16 Tx Channels Programmable FIFO Depth Verification Testbench Verilog User Testbenches Up to 512 Words Libero IDE Compatible Programmable Interrupt Generation VHDL and Verilog Rx and Tx Channels independently Up to 64 Words Configurable Label Memory Size Development System Rx and Tx Channels independently Complete ARINC 429 Rx/Tx Up to 256 Words Implementation Internal, Wrap-Around Testing Implemented in an APA600 Device Software Compatible with Legacy Devices Controlled Via an External Terminal Using Selectable Clock Speed Core8051 and RS232 Links Includes Line Driver and Receiver Components 1, 10, 16, or 20 MHz Selectable Data Rate on Each Channel 12.5 100 kbps Synthesis and Simulation Support Optional 50 kbps Directly Supported within the Actel Libero IDE CPU Interface Synthesis: Provides Direct CPU Access to Memory Synplicity TM Simple Interface to Core8051 Exemplar Memory Synopsys EDAC Support with RTAX-S Family Simulation ARINC 429 Bus Interface Vital-Compliant VHDL Simulators Supports Standard Line Drivers and Receivers OVI-Compliant Verilog Simulators Available as Integrated Tx and Rx Verification and Compliance Supported Families Actel-Developed Simulation Testbench Fusion Core Implemented on the ARINC 429 ProASIC 3/E Development System PLUS ProASIC Axcelerator RTAX-S September 2006 v5.0 1 2006 Actel CorporationARINC 429 Bus Interface Contents General Description .................................................... 2 RxHi Rx I/F ARINC 429 Overview .................................................. 2 Glue RxLo CPU CPU Logic Core429 Device Requirements ................................... 3 Interface TxHi Memory Requirements ............................................... 4 Tx I/F TxLo Core429 Overview ...................................................... 5 Default Mode ............................................................. 5 CoreARINC429 Functional Description ............................................... 5 Legacy Mode ............................................................... 7 Actel FPGA Core Parameters ......................................................... 8 I/O Signal Descriptions ............................................... 8 Figure 1 Typical Core429 SystemOne Tx and One Rx Default Mode Operation ......................................... 10 Legacy Operation ..................................................... 13 ARINC 429 Overview Status Register .......................................................... 15 ARINC 429 is a two-wire, point-to-point data bus that is CPU Interface Timing for Default Mode ................. 16 application-specific for commercial and transport Clock Requirements .................................................. 17 aircraft. The connection wires are twisted pairs. Words Core429 Verification ................................................ 17 are 32 bits in length and most messages consist of a Testbench .................................................................. 17 single data word. The specification defines the electrical Line Drivers ............................................................... 18 standard and data characteristics and protocols. Line Receivers ........................................................... 18 ARINC 429 uses a unidirectional data bus standard (Tx and Rx are on separate ports) known as the Mark 33 Loopback Interface ................................................... 18 Digital Information Transfer System (DITS). Messages are Development System ................................................ 18 transmitted at 12.5, 50 (optional), or 100 kbps to other Ordering Information .............................................. 19 system elements that are monitoring the bus messages. List of Changes ......................................................... 20 The transmitter is always transmitting either 32-bit data Datasheet Categories ............................................... 21 words or the Null state. The ARINC standard supports High, Low, and Null states (Figure 2). A minimum of four Null bits should be transmitted between ARINC words. No more than 20 receivers can be connected to a single bus (wire pair) and General Description no less than one receiver, though there will normally be Core429 provides a complete Transmitter (Tx) and more. Receiver (Rx). A typical system implementation using Core429 is shown in Figure 1. The core consists of three main blocks: Transmit, Receive, 12 3 4 5 6 8 910 32 Bit 7 Number and CPU Interface (Figure 1). Core429 requires High +5 connection to an external CPU. The CPU interface A Null 0 Leg Low 5 configures the transmit and receive control registers and initializes the label memory. The core interfaces to the High +5 Leg B Null 0 ARINC 429 bus through an external ARINC 429 line driver Low 5 and line receiver. A detailed description of the Rx 001 1 0 10 0 1 1 1 Data interface and Tx interface is provided in theFunctional Descriptio section on page 5. Figure 2 ARINC Standard External Components Figure 3 on page 3 shows the bit positions of ARINC There are two external components required for proper data. operation of Core429: Each ARINC word contains five fields: Standard ARINC 429 line driver Parity Standard ARINC 429 line receiver 2 v5.0