CEC1302D-C0-SZ

CEC1302 Low Power Crypto Embedded Controller Public Key Cryptographic Engine Product Features - Hardware support for RSA and Elliptic Curve ARM Cortex -M4 Processor Core public key algorithms - 32-Bit ARM v7-M Instruction Set Architecture - RSA keys length from 512 to 2048 bits - Hardware Floating Point Unit (FPU) - ECC Prime Field keys up to 256 bits - Single 4GByte Addressing Space (Von Neu- Cryptographic Features mann Model) - True Random Number Generator - Little-Endian Byte Ordering -1K bit FIFO - Bit-Banding Feature Included - Secure Boot from ROM - NVIC Nested Vectored Interrupt Controller - Hardware based root of trust - Up to 240 Individually-Vectored Interrupt Sources - Support Secure Firmware Updates Supported Two SPI Memory Interfaces - 8 Levels of Priority, Individually Assignable By Vector - 3-pin Full Duplex serial communication interface - Chip-Level Interrupt Aggregator supported, to - Two Private and Two Shared Chip Selects expand number of interrupt sources or reduce - DMA Support number of vectors Battery Backed (VCC0/VBAT) Resources - System Tick Timer - Power Fail Register - Complete ARM-Standard Debug Support - Power-Fail Status Register - JTAG-Based DAP Port, Comprised of SWJ-DP and - Battery backed 64 byte memory AHB-AP Debugger Access Functions Real Time Clock (RTC) - Full DWT Hardware Functionality: 4 Data - VCC0 (VBAT) Powered Watchpoints and Execution Monitoring - Full FPB Hardware Breakpoint Functionality: 6 - 32KHz Crystal Oscillator Execution Breakpoints and 2 Literal (Data) - 32KHz Clock output available under VCC1 Breakpoints power - Comprehensive ARM-Standard Trace Sup- - Time-of-Day and Calendar Registers port - Programmable Alarms - Full DWT Hardware Trace Functionality for - Supports Leap Year and Daylight Savings Watchpoint and Performance Monitoring Time - Full ITM Hardware Trace Functionality for Hibernation Timers Instrumented Firmware Support and Profiling General Purpose Analog to Digital Converter - Full ETM Hardware Trace Functionality for - 10-bit conversion precision Instruction Trace - 10-bit conversion per channel is completed in - Full TPIU Functionality for Trace Output less than 12us Communication 128K SRAM (Code and Data) - 5 ADC channels - 96K Optimized for Code - 10-bit Conversion with 2.9mV resolution - 0 to 3.3 VDC Conversion Range - 32K Optimized for Data - Optional continuous sampling at a programmable Multi-purpose AES Cryptographic Engine rate - Hardware support for ECB, CTR, CBC and - Internal Analog Voltage Reference (3.0V +/- OFB AES modes 1%) - Support for 128-bit, 192-bit and 256-bit key Watch Dog Timer length Four Programmable 16-bit and Two 32-bit Timers - DMA interface to SRAM, shared with Hash - Wake-capable Auto-reloading Timers engine Four Programmable Pulse-Width Modulator Out- Cryptographic Hash Engine puts - Support for SHA-1 & SHA-256 - Independent Clock Rates - DMA interface to SRAM, shared with AES - 16-Bit Duty Cycle Granularity engine - Operational in both Full on and Standby modes 2016 Microchip Technology Inc. DS00002022B-page 1CEC1302 2 Four I C/SMBus 2.0 Host Controllers Description - Allows Master or Dual Slave Operation The CEC1302 incorporates a high-performance 32-bit - Controllers are Fully Operational on Standby Cortex -M4 embedded microcontroller with 128 ARM Power 2 Kilobytes of SRAM and 32 Kilobytes of Boot ROM. It - DMA-driven I C Network Layer Hardware 2 communicates with the system host using the I2C bus. -I C Datalink Compatibility Mode - Multi-Master Capable The CEC1302 has two SPI memory interfaces that - Supports Clock Stretching allow the EC to read its code from external SPI flash - Programmable Bus Speeds memory: private SPI and/or shared SPI. The Shared - 400 KHz Fast-mode Capable SPI interface allows for EC code to be stored in a - 1 Mbps Fast-mode Plus Capable shared SPI chip. The private SPI memory interface pro- - Hardware Bus AccessFairnes Interface vides for a dedicated SPI flash that is only accessible - SMBus Time-outs Interface by the EC. -5 Ports The CEC1302 provides support for loading EC code - 2 Port Flexible Multiplexing from the private or shared SPI flash device on a VCC1 Keyboard Matrix Scan Interface power-on. Before executing the EC code loaded from a - 18 x 8 Interrupt/Wake Capable Multiplexed SPI Flash Device, the CEC1302 validates the EC code Keyboard Scan Matrix using a digital signature encoded according to PKCS - Row Predrive Option 1. The signature uses RSA-2048 encryption and Four Breathing/Blinking LED Interfaces SHA-256 hashing. This provides automated detection - Programmable Blink Rates of invalid EC code that may be a result of malicious or - Piecewise Linear Breathing LED Output Con- accidental corruption. It occurs before each boot of the troller host processor, thereby ensuring a HW based root of - Operational in EC Sleep States trust not easily thwarted via physical replacement Dual Fan Tachometer Inputs attack. RPM-Based Fan Speed Control Algorithm - Utilizes one TACH input and one PWM output The CEC1302 is directly powered by two separate sus- - 3% accurate from 500 RPM to 16k RPM pend supply planes (VBAT and VCC1) and senses the - Automatic Tachometer feedback runtime power plane (VCC) to provide Instant On and - Aging Fan or Invalid Drive Detection system power management functions. It also contains - Spin Up Routine an integrated VCC1 Reset Interface and a system - Ramp Rate Control Power Management Interface that supports low-power - RPM-based Fan Speed Control Algorithm states and can drive state changes as a result of hard- Glue Logic Functionality Supporting System Deep ware wake events. Sleep Integrated Power-on Reset Generator - VCC1 RST open drain output - Accepts External driven Reset Anti-Glitch Protection on Power-on All Blocks Support Low Power Sleep Modes General Purpose Input/Output Pins - Low Power - High Configurability Two pin Debug Port with standard 16C550A regis- ter interface BC-Link Interconnection Bus - One High Speed Bus Master Controller - Connects to a Microchip GPIO Expander Package - 144-pin WFBGA DS00002022B-page 2 2016 Microchip Technology Inc.