AT87C58X2-SLSUL

Features 80C52 Compatible 8051 pin and instruction compatible Four 8-bit I/O ports Three 16-bit timer/counters 256 bytes scratchpad RAM High-Speed Architecture 40 MHz 5V, 30MHz 3V X2 Speed Improvement capability (6 clocks/machine cycle) 8-bit CMOS 30 MHz 5V, 20 MHz 3V (Equivalent to 60 MHz 5V, 40 MHz 3V) Microcontroller Dual Data Pointer On-chip ROM/EPROM (16K-bytes, 32K-bytes) 16/32 Kbytes Programmable Clock Out and Up/Down Timer/Counter 2 Hardware Watchdog Timer (One-time enabled with Reset-Out) ROM/OTP Asynchronous port reset Interrupt Structure with 6 Interrupt sources TS80C54/58X2 4 level priority interrupt system Full duplex Enhanced UART TS87C54/58X2 Framing error detection Automatic address recognition AT80C54/58X2 Low EMI (inhibit ALE) Power Control modes AT87C54/58X2 Idle mode Power-down mode Power-off Flag Once mode (On-chip Emulation) Power supply: 4.5-5.5V, 2.7-5.5V o o Temperature ranges: Commercial (0 to 70 C) and Industrial (-40 to 85 C) Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 F1, CQPJ44 (window), CDIL40 (window) 1. Description TS80C54/58X2 is high performance CMOS ROM, OTP and EPROM versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C54/58X2 retains all features of the Atmel 80C51 with extended ROM/EPROM capacity (16/32 Kbytes), 256 bytes of internal RAM, a 6-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C54/58X2 a Hardware Watchdog Timer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism. The fully static design of the TS80C54/58X2 allows to reduce system power consump- tion by bringing the clock frequency down to any value, even DC, without loss of data. Rev. 4431E805104/06The TS80C54/58X2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. PDIL40 PLCC44 PQFP44 F1 VQFP44 1.4 ROM (bytes) EPROM (bytes) TS80C54X2 16k 0 TS80C58X2 32k 0 TS87C54X2 0 16k TS87C58X2 0 32k 2. Block Diagram (2) (2) (1) (1) XTAL1 ROM RAM /EPROM EUART XTAL2 Timer2 256x8 16/32Kx8 ALE/PROG C51 CORE IB-bus PSEN CPU EA/VPP (2) Timer 0 INT Parallel I/O Ports Watch RD Timer 1 Ctrl Dog (2) Port 0Port 1 Port 2 Port 3 WR (2) (2) (2) (2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 2 AT/TS8xC54/8X2 4431E805104/06 RESET T0 RxD TxD T1 INT0 INT1 P0 P1 Vcc P2 Vss P3 T2EX T2