Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Data Sheet Describes Mode 0 Operation Low-voltage and Standard-voltage Operation 1.8 (VCC = 1.8V to 5.5V) 20 MHz Clock Rate (5V) 64-byte Page Mode and Byte Write Operation Block Write Protection SPI Serial Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software EEPROMS Data Protection Self-timed Write Cycle (5 ms Max) 128K (16,384 x 8) High-reliability Endurance: 1 Million Write Cycles 256K (32,768 x 8) Data Retention: >100 Years Green (Pb/Halide-free/RoHS Compliant) Packaging Options Die Sales: Wafer Form, Waffle Pack, and Bumped Die AT25128B Description AT25256B The AT25128B/256B provides 131,072/262,144 bits of serial electrically-erasable pro- grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead SOIC, 8-lead TSSOP, 8-ball VFBGA and 8-lead UDFN pack- Preliminary ages. In addition, the entire family is available in 1.8V (1.8V to 5.5V). The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa- rate Erase cycle is required before Write. 8593CSEEPR8/09Figure 0-1. Pin Configurations 8-lead SOIC 8-lead TSSOP CS 1 8 VCC CS 1 8 VCC SO 2 7 HOLD SO 2 7 HOLD WP 3 6 SCK WP 3 6 SCK GND 4 5 SI GND 4 5 SI 8-lead UDFN 8-ball dBGA2 8 1 CS VCC 8 1 CS VCC HOLD 7 2 SO 7 2 SO HOLD SCK 6 3 WP 6 3 WP SCK SI 5 4 GND 5 4 GND SI Bottom View Bottom View Table 0-1. Pin Configurations Pin Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground V Power Supply CC WP Write Protect HOLD Suspends Serial Input NC No Connect Block Write protection is enabled by programming the status register with top , top or entire array of write protection. Separate Program Enable and Program Disable instructions are pro- vided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. 1. Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under Abso- Operating Temperature....................... 55C to +125C lute Maximum Ratings may cause perma- nent damage to the device. This is a stress Storage Temperature ........................ 65C to + 150C rating only and functional operation of the Voltage on Any Pin device at these or any other conditions with Respect to Ground............................. 1.0 V +7.0V beyond those indicated in the operational sections of this specification are not implied. Maximum Operating Voltage.................................6.25V Exposure to absolute maximum rating con- ditions for extended periods may affect DC Output Current ..............................................5.0 mA device reliability. 2 AT25128B/256B Preliminary 8593CSEEPR8/09