xr XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET N0VEMBER 2006 REV.1.2.0. FEATURES GENERAL DESCRIPTION Provides DS3/ E3 mapping/de-mapping for up to The XRT94L33 is a highly integrated SONET/SDH 3 tributaries through SONET STS-1 or SDH AU- terminator designed for E3/DS3/STS-1 3 and/or TUG-3/AU-4 containers mapping/de-mapping functions from either the STS-3 or STM-1 data stream. The XRT94L33 Generates and terminates SONET/SDH section, interfaces directly to the optical transceiver line and path layers The XRT94L33 processes the section, line and Integrated SERDES with Clock Recovery Circuit path overhead in the SONET/SDH data stream and also performs ATM and PPP PHY-layer Provides SONET frame scrambling and processing. The processing of path overhead bytes descrambling within the STS-1s or TUG-3s includes 64 bytes for Integrated Clock Synthesizer that generates 155 storing the J1 bytes. Path overhead bytes can be MHz and 77.76 MHz clock from an external accessed through the microprocessor interface or 12.96/19.44/77.76 MHz reference clock via serial interface. Integrated 3 E3/DS3/STS-1 De-Synchronizer The XRT94L33 uses the internal E3/DS3 De- circuit that de-jitter gapped clock to meet Synchronizer circuit with an internal pointer leak 0.05UIpp jitter requirements algorithm for clock smoothing as well as to remove the jitter due to mapping and pointer movements. Access to Line or Section DCC These De-Synchronizer circuits do not need any Level 2 Performance Monitoring for E3 and DS3 external clock reference for its operation. Supports mixing of STS-1E and DS3 or E3 and The SONET/SDH transmit blocks allow flexible DS3 tributaries insertion of TOH and POH bytes through both Hardware and Software. Individual POH bytes for UTOPIA Level 2 interface for ATM or level 2P for the transmitted SONET/SDH signal are mapped Packets either from the XRT94L33 memory map or from external interface. A1, A2 framing pattern, C1 byte E3 and DS3 framers for both Transmit and and H1, H2 pointer byte are generated. Receive directions The SONET/SDH receive blocks receive SONET Complete Transport/Section Overhead STS-3 signal or SDH STM-1 signal and perform the Processing and generation per Telcordia and necessary transport and path overhead processing. ITU standards The XRT94L33 provides a line side APS Single PHY and Multi-PHY operations supported (Automatic Protection Switching) interface by Full line APS support for redundancy offering redundant receive serial interface to be applications switched at the frame boundary. Loopback support for both SONET/SDH as well The XRT94L33 provides 3 mappers for performing as E3/DS3/STS-1 STS-1/VC-3 to STS-1/DS3/E3 mapping function, one for each STS-1/DS3/E3 framers. Boundary scan capability with JTAG IEEE 1149 A PRBS test pattern generation and detection is 8-bit microprocessor interface implemented to measure the bit-error performance. 3.3 V 5% Power Supply 5 V input signal A general-purpose microprocessor interface is tolerance included for control, configuration and monitoring. -40C to +85C Operating Temperature Range APPLICATIONS Available in a 504 Ball TBGA package Network switches Add/Drop Multiplexer W-DCS Digital Cross Connect Systems E CORPORATION 48720 KATO ROAD, FREMONT CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * WWW.EXAR.COM XRT94L33 xr Rev.1.2.0. 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Block Diagram of the XRT94L33 Telecom SONET/SDH SONET/SDH Boundry To OC12 Bus TOH POH Scan Interface OC3 Microprocessor To F.O. TxRx SDH MUX Interface DS3/E3 SONET/SDH ATM Jitter Attenuator Mapper POH DS3/E3 Processor & Framer Clock Smoothing PLCP PPP Telecom Processor Pointer Bus To DS3/E3 Justify Interface STS-1 Telecom HDLC Bus/ Controller T3/E3/HDLC STS-1 Tx/Rx Intf TOH & POH STS-1 Channel 0 DS3/E3 SONET/SDH ATM Jitter Attenuator Mapper POH DS3/E3 Processor & Framer PLCP Clock Smoothing PPP UTOPIA Telecom Processor Pointer II/IIp Bus To DS3/E3 Justify Interface Interface STS-1 Telecom HDLC Bus/ Controller T3/E3/HDLC STS-1 Tx/Rx Intf TOH & POH STS-1 Channel 1 DS3/E3 SONET/SDH ATM Jitter Attenuator Mapper DS3/E3 Processor POH & Framer PLCP Clock Smoothing PPP Telecom Processor Pointer Bus To DS3/E3 Justify Interface STS-1 Telecom HDLC Bus/ Controller T3/E3/HDLC STS-1 Tx/Rx Intf TOH & POH STS-1 Channel 2 ORDERING INFORMATION PART NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRT94L33IB 27 x 27 504 Lead TBGA -40C to +85C 2