LMS7002M FPRF MIMO Transceiver IC With Integrated Microcontroller On chip integrated microcontroller for simplified calibration, SUMMARY FEATURES tuning and control Field Programmable Radio Frequency (FPRF) chip Integrated clock PLL for flexible clock generation and Dual transceiver ideal for MIMO distribution User programmable on the fly User definable analog and digital filters for customised Continuous coverage of the 100 kHz - 3.8 GHz RF frequency filtering range RF and base band Received Signal Strength Indicator (RSSI) Digital interface to baseband with on chip integrated 12 bit On chip integrated temperature sensor D/A and A/D converters 261 pin aQFN 11.5x11.5 mm package Programmable RF modulation bandwidth up to Power down option 160 MHz using analog interface Serial port interface Programmable RF modulation bandwidth up to Low power consumption, typical 880mW in full 2x2 MIMO 96 MHz using digital interface mode (550mW in SISO mode) using external LDOs Supports both TDD and full duplex FDD Multiple bypass modes for greater flexibility LimeLight digital IQ interface JEDEC JESD207 TDD and FDD compliant APPLICATIONS Transceiver Signal Processor block employs advanced techniques for enhanced performance Broad band wireless communications Single chip supports 2x2 MIMO. Multiple chips can be used GSM, CDMA2000, TD-SCDMA, WCDMA/HSPA, LTE to implement higher order MIMO IEEE xxx.xxx radios On-chip RF calibration circuitry WiFi operating in the Whitespace frequencies Fully differential baseband signals, analog IQ Software Defined Radio (SDR) Few external components Cognitive Radio Low voltage operation, 1.25, 1.4 and 1.8V. Integrated LDOs Unmanned Aerial Vehicle (UAV) to run on a single 1.8V supply voltage Other Whitespace applications Figure 1: Functional block diagram Document version: 3.1r00 LMS7002M FPRF MIMO Transceiver IC The LMS7002M provides an RF loop back option which enables the TX GENERAL DESCRIPTION RF signal to be fed back into the baseband for calibration and test LMS7002M is a fully integrated, multi-band, multi-standard RF purposes. The RF loop back signal is amplified by the loopback transceiver that is highly programmable. It combines Low Noise amplifier in order to increase the dynamic range of the loop. Amplifiers (RXLNA), TX Power Amplifier Drivers (TXPAD) receiver/transmitter (RX/TX) mixers, RX/TX filters, synthesizers, RX There are two additional loop back options implemented, one is an gain control, TX power control, the analog-to-digital and digital-to- analog base band (BB) loop back and another is a digital loop back analog convertors (ADC/DACs) and has been designed to require very (DLB) as shown in Figure 1. The analog loop back is intended for few external components. testing while the DLB can be used to verify the LMS7002M connectivity to base band, FPGA, DSP or any other digital circuitry. The top level architecture of LMS7002M transceiver is shown in Figure 1. The chip contains two transmit and two receive chains for achieving a On the receive side, three separate inputs are provided each with a Multiple In Multiple Out (MIMO) platform. Both transmitters share one dedicated LNA optimised for narrow or wide band operation. Each port PLL and both receivers share another. Transmit and receive chains are RF signal is first amplified by a programmable low noise amplifier all implemented as zero Intermediate Frequency (zero IF or ZIF) (RXLNA). The RF signal is then mixed with the receive PLL (RXPLL) architectures providing up to 160MHz RF modulation bandwidths output to directly down convert to baseband. AGC steps can be (equivalent to 80MHz baseband IQ bandwidth). For the purpose of implemented by a BB trans-impedance amplifier (RXTIA) prior to the simplifying this document, the explanation for the functionality and programmable bandwidth low pass channel select / anti alias filters performance of the chip is based on one transmit and one receive (RXLPF). The received IQ signal is further amplified by a programmable circuitry, given that the other two work in exact the same manner. gain amplifier RXPGA. DC offset is applied at the input of RXTIA to prevent saturation and to preserve the receive ADCs dynamic range. On the transmit side, In-phase and Quadrature IQ DAC data samples, The resulting analog receive IQ signals are converted into the digital from the base band processor, are provided to the LMS7002M via the domain with on-chip receive ADCs. Following the ADCs, the signal LimeLight digital IQ interface. LimeLight implements the JESD207 conditioning is performed by the digital Transceiver Signal Processor standard IQ interface protocol as well as de facto IQ multiplexed (TSP) and the resulting signals are then provided to the BB via the standard. JESD207 is Double Data Rate (DDR) by definition. In IQ LimeLight digital IQ interface. multiplexed mode LimeLight also supports Single Data Rate (SDR). The IQ samples are then pre-processed by the digital Transceiver The analog receive signals can also be provided off chip at RXOUTI Signal Processor (TSP) for minimum analog / RF distortion and applied and RXOUTQ pins by closing the RXOUT switch. In this case it is to the on chip transmit DACs. The DACs generate analog IQ signals possible to power down the on chip ADCs/TSP and use external parts which are provided for further processing to the analog/RF section. which can be very useful for more resource demanding applications or Transmit low pass filters (TXLPF) remove the images generated by where higher signal resolution is required. A similar option is also zero hold effect of the DACs, as well as the DAC out-of-band noise. The available on the TX side where the analog signal can be processed by analog IQ signals are then mixed with the transmit PLL (TXPLL) output external components. The on chip DACs/TSP can be powered down to produce a modulated RF signal. This RF signal is then amplified by and analog inputs can be provided at TXINI and TXINQ pins. one of two separate / selectable power amplifier drivers and two open- drain differential outputs are provided as RF output for each MIMO There is on chip integrated temperature sensor which base band path. modem can read via the SPI and trigger re-calibration of the chip if significant chip/ambient temperature change is observed. Parameter Min. Typ. Max. Unit Condition/Comment Operating Temperature Range -40 25 85 C Storage Temperature Range -65 25 125 C 30 3800 Operating Frequency Range MHz 0.1 3800 Extended by TSP NCOs 48 Through digital interface (MIMO) RF Modulation Bandwidth 96 MHz Through digital interface (SISO) 160 Through analog interface Frequency Resolution 24.8 Hz Using 52 MHz PLL reference clock Analog Supply Voltage, High (VDDAH) 1.71 1.8 1.89 V Used for TXPAD Analog Supply Voltage, Medium Generated using integrated low-dropout regulators 1.33 1.4 1.47 V (VDDAM) (LDOs) Analog Supply Voltage, Low (VDDAL) 1.2 1.25 1.3 V Generated using integrated LDOs Digital Core Supply Voltage 1.1 1.2 1.3 V Generated using integrated LDOs Digital Peripheral (IO) Supply Voltage 1.7 2.5 3.6 V At -7 dBm output power, 2x2 MIMO, including the DACs TX Supply Current 350 mA and TSP RX Supply Current 420 mA For 2x2 MIMO, including the ADCs and TSP Maximum RF Output Power 0 dBm Continuous Wave PLL Reference Clock 10 52 MHz Measured at TX RF output or RX RF input Reference and Other Spurs Level -100 dBm IQ Imbalance Image -70 dBc After calibration Interpolation/Decimation digital filters 108 dB stop band suppression Table 1: General specifications LMS7002M 2