IP-100GEMAC

40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Last updated for Altera Complete Design Suite: 14.1 UG-01088 101 Innovation Drive Subscribe 2014.12.15 San Jose, CA 95134 Send Feedback www.altera.comTOC-2 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Contents About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function.....1-1 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features...........................................1-3 40-100GbE IP Core Device Family and Speed Grade Support..............................................................1-4 Device Family Support.................................................................................................................... 1-4 40-100GbE IP Core Device Speed Grade Support...................................................................... 1-5 IP Core Verification.....................................................................................................................................1-6 Simulation Environment................................................................................................................ 1-7 Hardware Testing.............................................................................................................................1-7 Performance and Resource Utilization.....................................................................................................1-7 Resource Utilization for 40GbE IP Cores.....................................................................................1-7 Resource Utilization for 100GbE IP Cores.................................................................................1-12 Release Information...................................................................................................................................1-18 Getting Started.................................................................................................... 2-1 Installing and Licensing IP Cores.............................................................................................................. 2-2 OpenCore Plus IP Evaluation........................................................................................................ 2-2 Specifying the 40-100GbE IP Core Parameters and Options................................................................ 2-3 IP Core Parameters......................................................................................................................................2-3 Files Generated for the 40-100GbE IP Core...........................................................................................2-10 Simulating the IP Core..............................................................................................................................2-10 Integrating Your IP Core in Your Design.............................................................................................. 2-11 Pin Assignments.............................................................................................................................2-11 External Transceiver Reconfiguration Controller.....................................................................2-11 Placement Settings for the 40-100GbE IP Core.........................................................................2-14 40-100GbE IP Core Testbenches............................................................................................................. 2-14 Testbenches with Adapters...........................................................................................................2-15 Testbenches without Adapters.....................................................................................................2-18 Understanding the Testbench Behavior..................................................................................... 2-19 Simulating the 40-100GbE IP Core With the Testbenches..................................................................2-20 Generating the 40-100GbE Testbench........................................................................................2-21 Simulating with the Modelsim Simulator...................................................................................2-21 Simulating with the NCSim Simulator....................................................................................... 2-21 Simulating with the VCS Simulator............................................................................................ 2-21 Testbench Output Example: 40GbE IP Core with Adapters................................................... 2-21 Testbench Output Example: 100GbE IP Core with Adapters................................................. 2-23 Compiling the Full Design and Programming the FPGA....................................................................2-24 Initializing the IP Core..............................................................................................................................2-24 Functional Description....................................................................................... 3-1 High Level System Overview......................................................................................................................3-2 40-100GbE MAC and PHY Functional Description.............................................................................. 3-2 Altera Corporation