TLE 6244X 18 Channel Smart Lowside Switch ASSP for Powertrain Data Sheet Features Short Circuit Protection Overtemperature Protection Overvoltage Protection 16 bit Serial Data Input and Diagnostic Output (2 bit/chan. acc. SPI Protocol) Direct Parallel Control of 16 channels for PWM Applications Low Quiescent Current PG-MQFP-64-10 Compatible with 3.3V Microcontrollers Electrostatic discharge (ESD) Protection Green Product (RoHS-compliant) AEC qualified General description 18-fold Low-Side Switch (0.35 to 1 ) in Smart Power Technology (SPT) with a Serial Pe- ripheral Interface (SPI) and 18 open drain DMOS output stages. The TLE6244X is protected by embedded protection functions and designed for automotive and industrial applications. The output stages are controlled via SPI Interface. Additionally 16 of the 18 channels can be controlled direct in parallel for PWM applications. Therefore the TLE6244X is particularly suitable for engine management and powertrain systems. VS V BB IN1 Protection IN2 as Ch. 1 Functions as Ch. 1 LOGIC as Ch. 1 as Ch. 1 OUT1 as Ch. 1 Output Stage as Ch. 1 IN15 IN16 as Ch. 1 16 16 1 SCLK Output Control SI Serial Interface OUT18 Buffer SPI SO GND Data Sheet 1 V7, 2007-06-11 TLE 6244X 1. Description 1.1 Short Description This circuit is available in PG-MQFP-64 package or as chip. 1.1.1 Features of the Power Stages Nominal Current static current limita- Clamping R at T = 25C on,max J tion enabled by SPI 2.2A 400m - 70V OUT1, 2, 5, 6 2.2A 380m - 70V OUT3, OUT4 1.1A 780m - 45V OUT7, OUT8 2.2A 380m X 45V OUT9, OUT10 2.2A 380m - 45V OUT11...OUT14 3.0A 280m X 45V OUT15, OUT16 1.1A 780m X 45V OUT17, OUT18 *) *) only serial control possible (via SPI) Parallel connection of power stages is possible (see 1.13) Internal short-circuit protection Phase relation: non-inverting (exception: IN8->OUT8 is inverting) 1.1.2 Diagnostic Features The following types of error can be detected: Short-circuit to U (SCB) Batt Short-circuit to ground (SCG) Open load (OL) Overtemperature (OT) Individual detection for each output. Serial transmission of the error code via SPI. 1.1.3 VDD-Monitoring Low signal at pin ABE and shut-off of the power stages if VDD is out of the permitted range. Exception: If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage detection and not by undervoltage detection. The state of VDD can be read out via SPI. 1.1.4 sec-bus Alternatively to the parallel and SPI control of the power stages, a high speed serial bus inter- face can be configured as control of the power stages OUT1...OUT7 and OUT9...OUT16. 1.1.5 Power Stage OUT8 OUT8 can be controlled by SPI or by the pin IN8 only. When controlled by IN8 this power stage is functional if the voltage at the pin VDD is above 3,5V. OUT8 will not be reset by RST. In SPI mode the power stage is fully supervised by the VDD-monitor. Data Sheet 2 V7, 2007-06-11