CYV15G0204TRB-BGXC

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYV15G0204TRB Independent Clock HOTLink II Dual Serializer and Dual Reclocking Deserializer Features Functional Description Second-generation HOTLink technology The CYV15G0204TRB Independent Clock HOTLink II Dual Serializer and Dual Reclocking Deserializer is a point-to-point Compliant to SMPTE 292M and SMPTE 259M video or point-to-multipoint communications building block enabling standards transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. Dual-channel video serializer plus dual channel video It supports signaling rates in the range of 195 to 1500 Mbps reclocking deserializer per serial link. All transmit and receive channels are 195- to 1500-Mbps serial data signaling rate independent and can operate simultaneously at different Simultaneous operation at different signaling rates rates. Each transmit channel accepts 10-bit parallel characters Supports reception of either 1.485 or 1.485/1.001 Gbps data in an Input Register and converts them to serial data. Each rate with the same training clock receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Supports half-rate and full-rate clocking Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1 Internal phase-locked loops (PLLs) with no external PLL illustrates typical connections between independent video components co-processors and corresponding CYV15G0204TRB chips. Selectable differential PECL-compatible serial inputs The CYV15G0204TRB satisfies the SMPTE 259M and Internal DC-restoration SMPTE 292M compliance as per SMPTE EG34-1999 Patho- logical Test Requirements. Redundant differential PECL-compatible serial outputs No external bias resistors required As a second-generation HOTLink device, the Signaling-rate controlled edge-rates CYV15G0204TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining Internal source termination serial-link compatibility (data and BIST) with other HOTLink Synchronous LVTTL parallel interface devices. Each transmit (TX) channel of the CYV15G0204TRB HOTLink II device accepts scrambled 10-bit transmission JTAG boundary scan characters. These characters are serialized and output from Built-In Self-Test (BIST) for at-speed link testing dual Positive ECL (PECL) compatible differential trans- mission-line drivers at a bit-rate of either 10- or 20-times the Link Quality Indicator input reference clock for that channel. Analog signal detect Digital signal detect Low-power 2.5 W at 3.3 V typical Single 3.3 V supply Thermally enhanced BGA Pb-free package option available 0.25 BiCMOS technology Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-02101 Rev. *G Revised August 18, 2017