CY7C68023/CY7C68024 EZ-USB NX2LP USB 2.0 NAND Flash Controller EZ-USB NX2LP USB 2.0 NAND Flash Controller 43-mA typical active current Features Space-saving and Pb-free 56-QFN package (8 mm 8 mm) High-Speed (480-Mbps) or Full-Speed (12-Mbps) USB support Support for board-level manufacturing test through USB Both common NAND page sizes supported interface 512 bytes Up to 1 Gbit capacity 3.3-V NAND flash operation 2K bytes Up to 8 Gbit capacity NAND flash power management support Eight chip enable pins Up to eight NAND flash single device chips Introduction Up to four NAND flash dual-device chips Industry-standard ECC NAND flash correction The EZ-USB NX2LPNX2LPimplements a USB 2.0 NAND Flash controller. This controller adheres to the Mass Storage 1-bit error correction per 256 bytes Class Bulk-Only Transport Specification. The USB port of the 2-bit error detection per 256 bytes NX2LP is connected to a host computer directly or through the Industry-standard (SmartMedia) Page Management for Wear downstream port of a USB hub. The Host software issues Leveling Algorithm, Bad Block Handling, and Physical to commands and data to the NX2LP and receives the status and Logical management data from the NX2LP using the standard USB protocol. Supports 8-bit NAND flash interfaces The NX2LP supports industry-leading 8-bit NAND flash interfaces and both common NAND page sizes of 512 and 2k Supports 30 ns, 50 ns, and 100 ns NAND flash timing bytes. Eight chip enable pins allow the NX2LP to be connected to up to eight single or four dual-device NAND flash chips. Complies with the USB Mass Storage Class Specification Revision 1.0 Certain NX2LP features are configurable, enabling the NX2LP to meet the needs of different design requirements. CY7C68024 complies with the USB 2.0 Specification for Bus-Powered Devices (TID 40460274) NX2LP Block Diagram Write Protect Chip Reset LED2 LED1 24 MHz PLL Xtal EZ-USB NX2LP Internal Control Logic Control NAND Control Signals NAND Flash Interface Chip Enable Signals Logic Smart HS/ VBUS USB 2.0 Data 8-bit Data Bus FS USB D+ Xceiver Engine D- Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-08055 Rev. *H Revised September 23, 2014CY7C68023/CY7C68024 Pin Assignments Figure 1. 56-pin QFN R B1 1 42 RESET R B2 2 41 GND AVCC 3 40 N/C XTALOUT 4 39 N/C XTALIN 5 38 WP SW AGND 6 37 Reserved AVCC 7 36 LED2 DPLUS 8 35 LED1 DMINUS 9 34 ALE AGND 10 33 CLE VCC 11 32 VCC GND 12 31 RE1 N/C 13 30 RE0 GND 14 29 WE Pin Descriptions Pin Name Type Default State at Startup Description 1 1 R B1 I Z Ready/Busy 1 (2.2k to 4k pull up resistor is required) 2 R B2 I Z Ready/Busy 2 (2.2k to 4k pull up resistor is required) 3 AVCC PWR PWR Analog 3.3 V supply 4 XTALOUT Xtal N/A Crystal output 5 XTALIN Xtal N/A Crystal input 6 AGND GND GND Ground 7 AVCC PWR PWR Analog 3.3 V supply 8 DPLUS I/O Z USB D+ 9 DMINUS I/O Z USB D- 10 AGND GND GND Ground 11 VCC PWR PWR 3.3 V supply 12 GND GND GND Ground 13 N/C N/A N/A No connect 14 GND GND GND Ground 15 Reserved N/A N/A Must be tied HIGH (no pull up resistor required) Note 1. A sign after the pin name indicates that it is an active LOW signal. Document : 38-08055 Rev. *H Page 2 of 10 Reserved 15 56 GND Reserved 16 55 VCC VCC 17 54 N/C DD0 18 53 GND DD1 19 52 CE7 DD2 20 51 CE6 DD3 21 50 CE5 DD4 22 49 CE4 DD5 23 48 CE3 DD6 24 47 CE2 DD7 25 46 CE1 GND 26 45 CE0 VCC 27 44 Reserved GND 28 43 VCC