CY7C1470BV25 CY7C1472BV25 72-Mbit (2M 36/4M 18) Pipelined SRAM with NoBL Architecture 72-Mbit (2M 36/4M 18) Pipelined SRAM with NoBL Architecture Features Functional Description Pin-compatible and functionally equivalent to ZBT The CY7C1470BV25 and CY7C1472BV25 are 2.5 V, 2M 36/4M 18 synchronous pipelined burst SRAMs with No Supports 250 MHz bus operations with zero wait states Bus Latency (NoBL) logic, respectively. They are designed Available speed grades are 250, 200, and 167 MHz to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25 and CY7C1472BV25 Internally self-timed output buffer control to eliminate the need are equipped with the advanced (NoBL) logic required to enable to use asynchronous OE consecutive read or write operations with data being transferred Fully registered (inputs and outputs) for pipelined operation on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write Byte Write capability transitions. The CY7C1470BV25 and CY7C1472BV25 are pin-compatible and functionally equivalent to ZBT devices. Single 2.5 V power supply All synchronous inputs pass through input registers controlled by 2.5 V I/O supply (V ) DDQ the rising edge of the clock. All data outputs pass through output Fast clock-to-output times registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when 3.0 ns (for 250-MHz device) deasserted suspends operation and extends the previous clock Clock Enable (CEN) pin to suspend operation cycle. Write operations are controlled by the Byte Write Selects (BW BW for CY7C1470BV25 and BW BW for Synchronous self-timed writes a d a b CY7C1472BV25) and a Write Enable (WE) input. All writes are CY7C1470BV25 available in JEDEC-standard Pb-free 100-pin conducted with on-chip synchronous self-timed write circuitry. TQFP and Pb-free 165-ball FBGA package. CY7C1472BV25 Three synchronous Chip Enables (CE , CE , CE ) and an 1 2 3 available in JEDEC-standard Pb-free 100-pin TQFP asynchronous Output Enable (OE) provide for easy bank IEEE 1149.1 JTAG Boundary Scan compatible selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data Burst capability linear or interleaved burst order portion of a write sequence. ZZ Sleep Mode option and Stop Clock option For a complete list of related documentation, click here. Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 3.0 3.0 3.4 ns Maximum Operating Current 450 450 400 mA Maximum CMOS Standby Current 120 120 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-15032 Rev. *O Revised February 7, 2018CY7C1470BV25 CY7C1472BV25 Logic Block Diagram CY7C1470BV25 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U T E A T P N P U T U T S ADV/LD A T WRITE REGISTRY E R MEMORY AND DATA COHERENCY S B BW a WRITE E DQ s ARRAY CONTROL LOGIC G U DRIVERS A T DQ Pa BW b I F BW c E DQ Pb M S F BW d E DQ Pc T P E E DQ Pd R R S WE R S I S E N E G INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1472BV25 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 A0 BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U ADV/LD A T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY WRITE DQ s BW a E ARRAY S U CONTROL LOGIC G DRIVERS A F T DQ Pa I M E F BW b S DQ Pb P E E T S R R E S I R N WE S G E E INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Document Number: 001-15032 Rev. *O Page 2 of 29