GS4576C18GM-25I

GS4576C09/18/36GM 533 MHz300 MHz 144-Ball FBGA 64M x 9, 32M x 18, 16M x 36 2.5 V V EXT Commercial Temp 1.8 V V DD 576Mb CIO Low Latency DRAM (LLDRAM II) Industrial Temp 1.5 V or 1.8 V V DDQ Features Introduction Pin- and function-compatible with Micron RLDRAM II The GSI Technology 576Mb Low Latency DRAM 533 MHz DDR operation (1.067Gb/s/pin data rate) (LLDRAM II) is a high speed memory device designed for 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) high address rate data processing typically found in networking 16M x 36, 32M x 18, and 64M x 9 organizations available and telecommunications applications. The 8-bank architecture 8 banks and low tRC allows access rates formerly only found in Reduced cycle time (15 ns at 533 MHz) SRAMs. Address Multiplexing (Nonmultiplexed address option available) The Double Data Rate (DDR) I/O interface provides high SRAM-type interface bandwidth data transfers, clocking out two beats of data per Programmable Read Latency (RL), row cycle time, and burst clock cycle at the I/O balls. Source-synchronous clocking can sequence length be implemented on the host device with the provided free- Balanced Read and Write Latencies in order to optimize data running data output clock. bus utilization Data mask for Write commands Commands, addresses, and control signals are single data rate Differential input clocks (CK, CK) signals clocked in by the True differential input clock Differential input data clocks (DKx, DKx) transition, while input data is clocked in on both crossings of On-chip DLL generates CK edge-aligned data and output the input data clock(s). data clock signals Data valid signal (QVLD) Read and Write data transfers always in short bursts. The burst 32 ms refresh (16K refresh for each bank 128K refresh length is programmable to 2, 4 or 8 by setting the Mode command must be issued in total each 32 ms) Register. 144-ball FBGA package HSTL I/O (1.5 V or 1.8 V nominal) The device is supplied with 2.5 V V and 1.8 V V for the EXT DD 25 60 matched impedance outputs core, and 1.5 V or 1.8 V for the HSTL output drivers. 2.5 V V , 1.8 V V , 1.5 V or 1.8 V V I/O EXT DD DDQ On-die termination (ODT) R Internally generated row addresses facilitate bank-scheduled TT refresh. Commercial and Industrial Temperature Commercial (+0 T +95C) C The device is delivered in an efficient FBGA 144-ball package. Industrial (40 T +95C) C Rev: 1.00b 8/2018 1/61 2017, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS4576C09/18/36GM 64M x 9 Mb Ball Assignments144-Ball FBGATop View 1 2 3 4 5 6 7 8 9 10 11 12 V V V V V V A TMS TCK REF SS EXT SS SS EXT 3 3 3 V V V V B DQ0 DD DNU DNU SS SS DNU DD 3 3 3 V V V V C DQ1 DNU DNU DNU TT DDQ DDQ TT 1 3 3 V V V D QK0 QK0 A22 DNU DNU SS SS SS 3 3 3 V V E A21 DQ2 A20 DNU DNU DDQ DDQ DNU 3 3 3 V V F A5 DQ3 QVLD DNU DNU DNU SS SS V V G A8 A6 A7 A2 A1 A0 DD DD V V V V H B2 A9 A4 A3 SS SS SS SS 2 2 V V V V J B0 CK NF NF DD DD DD DD V V V V K DK DK B1 CK DD DD DD DD V V V V L REF CS A14 A13 SS SS SS SS V V M WE A16 A17 A12 A11 A10 DD DD 3 3 3 V V N A18 DQ4 A19 DNU DNU SS SS DNU 3 3 3 V V P A15 DQ5 DM DNU DNU DDQ DDQ DNU 3 3 3 V V V V R DQ6 SS DNU DNU SS SS DNU SS 3 3 3 T V V V DQ7 V TT DNU DNU DDQ DDQ DNU TT 3 3 3 V V V V U DQ8 DD DNU DNU SS SS DNU DD V V ZQ V V V V TDO TDI REF EXT SS SS EXT Notes: 1. Reserved for future use. This pin may be connected to ground. 2. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND. 3. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND. Rev: 1.00b 8/2018 2/61 2017, GSI Technology Specifications cited are subject to change without notice. For latest documentation see