AFCT-5943LZ

AFCT-5943LZ, AFCT-5943ALZ Single Mode SFF Transceivers for SONET OC-48/SDH STM-16 Multirate Operation (Part of the Avago Technologies METRAK family) Data Sheet Description Features Multirate operation from 125 Mb/s to 2.7 Gb/s The AFCT-5943xxZ are high performance, cost effective modules for serial optical data communications applica- AFCT-5943LZ/ALZ: Links of 2 km with 9/125 m tions that range from 125 Mb/s to 2.7 Gb/s. They are de- single mode fiber (SMF) signed to provide SONET/SDH compliant links at 2488 Multisourced 2 x 5 package style with LC receptacle Mb/s for short reach links. Single +3.3 V power supply The modules are designed for single mode bfi er and Temperaturerange: operate at a nominal wavelength of 1300 nm. They in- AFCT-5943LZ: 0C to +70C corporate high performance, reliable, long wavelength AFCT-5943ALZ: -40C to +85C optical devices and proven circuit technology to give Wave solder and aqueous wash process compatible long life and consistent service. Manufactured in an ISO9002 certified facility The transmitter section of the AFCT-5943LZ/ALZ incor- RoHS compliant porates a 1300 nm Fabry Perot (FP) laser. The transmit- Fully Class 1 CDRH/IEC 825 compliant ter has full IEC 825 and CDRH Class 1 eye safety. Compliant with ITU-T G.957, STM-16, I-16 and S-16.1 Optical Interfaces For each device the receiver section uses an MOVPE grown planar SEDET PIN photodetector for low dark AFCT-5943LZ/ALZ: with EMI shield current and excellent responsivity. Receiver output squelch function enabled A positive ECL logic interface simplifies interface to ex - Applications ternal circuitry. SONET/SDH equipment interconnect The transceivers are supplied in the new industry stan- Multirate Client Interface on Metro Gateways and dard 2 x 5 DIP style package with the LC fiber connector Edge Switches interface and is footprint compatible with SFF Multi Source Agreement (MSA).Functional Description Receiver Section Design The receiver section for the AFCT-5943xxZ contains an Figure 1 also shows a filter function which limits the InGaAs/InP photo detector and a preamplifier mounted bandwidth of the preamp output signal. The filter is de - in an optical subassembly. This optical subassembly signed to bandlimit the preamp output noise and thus is coupled to a postamp/decision circuit on a circuit improve the receiver sensitivity. board. The design of the optical assembly is such that it These components will reduce the sensitivity of the re- provides better than 27 dB Optical Return Loss (ORL). ceiver as the signal bit rate is increased above 2.7 Gb/s. The postamplifier is ac coupled to the preamplifier as Noise Immunity illustrated in Figure 1. The coupling capacitors are large enough to pass the SONET/SDH test pattern at 155 Mb/ The receiver includes internal circuit components to s, 622 Mb/s and 2488 Mb/s without significant distor - filter power supply noise. However under some condi - tion or performance penalty. For multirate applications tions of EMI and power supply noise, external power the sensitivity will meet the maximum SONET specifica - supply filtering may be necessary (see Application Sec - tion for OC48 across all datarates (-19 dBm), also for DC tion). balanced codes, e.g. 8B/10B. For codes which have a significantly lower frequency content, jitter and pulse The Signal Detect Circuit distortion could be degraded. The signal detect circuit works by sensing the peak level The receiver outputs are squelched at Signal Detect of the received signal and comparing this level to a ref- deasserts. That is, when the light input decreases to erence. The SD output is low voltage TTL. typical -27 dBm or less, the Signal Detect deasserts i.e. the SD Output goes to a PECL low state. This forces the DATA OUT and DATA OUT Bar to go PECL levels high and low respectively. DATA OUT FILTER TRANS- PECL IMPEDANCE OUTPUT PRE- AMPLIFIER BUFFER AMPLIFIER DATA OUT GND TTL SIGNAL SD OUTPUT DETECT BUFFER CIRCUIT Figure 1. Receiver Block Diagram 2