PI6ULS5V9515AWEX

PI6ULS5V9515A I2C Bus/SMBus Repeater drivers on and off. This can be used to isolate a badly Features behaved slave on power-up until after the system power- 2 2 channel, bidirectional buffer up reset. It should never change state during an I C-bus 2 operation because disabling during a bus operation will I C-bus and SMBus compatible hang the bus and enabling part way through a bus cycle Operating supply voltage range of 2.3 V to 3.6 V 2 could confuse the I C-bus parts being enabled. The Active HIGH repeater enable input enable pin should only change state when the global bus and the repeater port are in an idle state to prevent Open-drain input/outputs system failures. Lock-up free operation The output low levels for sides are approximately 0.5 Supports arbitration and clock stretching across the V, but the input voltage of each internal buffer must be 70 mV lower (0.43V) or even more lower. When the repeater output internally is driven low the low is not recognized 2 Accommodates Standard-mode and Fast-mode I C- as a low by the input.. This prevents a lockup condition bus devices and multiple masters from occurring when the input low condition is released. 2 Two or more PI6ULS5V9515A devices cant be Powered-off high-impedance I C-bus pins used in series. The PI6ULS5V9515A design does not 2 5.5 V tolerant I C-bus and enable pins allow this configuration. Since there is no direction pin, slightly different valid low-voltage levels are used to 0 Hz to 400 kHz clock frequency (the maximum avoid lockup conditions between the input and the system operating frequency may be less than 400 output of each repeater. A valid low applied at the input kHz because of the delays added by the repeater) of a PI6ULS5V9515A will be propagated as a buffered low with a slightly higher value on the output. When this ESD protection exceeds 4KV HBM per JESD22- buffered low is applied to another PI6ULS5V9515A- A114 type device in series, the second device does not Package: MSOP-8, SOIC-8 and DFN2x3-8L recognize it as a valid low and will not propagate it as a buffered low again. The device contains a power-up control circuit that Description sets an internal latch to prevent the output circuits The PI6ULS5V9515A is a CMOS integrated circuit from becoming active until Vcc is at a valid level (Vcc = 2 intended for I C bus and SMBus systems applications. 2.3 V). 2 The device contains two identical bidirectional open- As with the standard I C system, pull-up resistors are 2 drain buffer circuits that enable I C and similar bus required to provide the logic-high levels on the buffered systems to be extended without degradation of system bus. The PI6ULS5V9515A has standard open-collector 2 performance. configuration of the I C bus. The size of these pull-up The PI6ULS5V9515A enables the system designer resistors depends on the system, but each side of the to isolate two halves of a bus for both voltage and repeater must have a pull-up resistor. The device is 2 2 capacitance, accommodating more I C devices or longer designed to work with Standard mode and Fast mode I C 2 trace length. It also permits extension of the I C-bus by devices in addition to SMBus devices. Standard mode 2 2 providing bidirectional buffering for both the data (SDA) I C devices only specify 3mA in a generic I C system, and the clock (SCL) lines, thus allowing two buses of where Standard mode devices and multiple masters are 2 400 pF to be connected in an I C application. possible. Under certain conditions, higher termination The PI6ULS5V9515A has an EN pin to turn the currents can be used. All trademarks are property of their respective owners. www.diodes.com 1/18/2017 2017-01-0006 PT0455-4 1 PI6ULS5V9515A Pin Configuration MSOP-8 and SOIC-8 TDFN2x3-8L(Top View) Pin Description Pin No Name Description 1 n.c. Not connected 2 SCL0 serial clock port 0 bus 3 SDA0 serial data port 0 bus 4 GND supply ground (0 V) 5 EN active HIGH repeater enable input 6 SDA1 serial data port 1 bus 7 SCL1 serial clock port 1 bus 8 V supply voltage (2.3 V to 3.6 V) CC Block Diagram EN Function SCL0 = SCL1 H SDA0 = SDA1 L disabled Figure 1:Block Diagram All trademarks are property of their respective owners. www.diodes.com 1/18/2017 2017-01-0006 PT0455-4 2